ATMEGA163L-4AC Atmel, ATMEGA163L-4AC Datasheet - Page 74

• Manufacturer Part Number: ATMEGA163L-4AC
• Description: IC AVR MCU 16K A/D 2.7V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163L-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART Control
UART I/O Data Register – UDR
UART Control and Status
Register A – UCSRA
74
ATmega163(L)
set), the 9th bit is one for an address byte and zero for a data byte, whereas the stop bit
is always high.
The following procedure should be used to exchange data in Multi-Processor Communi-
cation mode:
1. All Slave MCUs are in Multi-Processor Communication mode (MPCM in UCSRA
2. The Master MCU sends an address byte, and all slaves receive and read this
3. Each Slave MCU reads the UDR Register and determines if it has been
4. For each received data byte, the receiving MCU will set the Receive Complete
5. After the last byte has been transferred, the process repeats from step 2.
The UDR Register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data Register is written.
When reading from UDR, the UART Receive Data Register is read.
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift
Register to UDR. The bit is set regardless of any detected framing errors. When the
RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when
RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception
is used, the UART Receive Complete Interrupt routine must read UDR in order to clear
RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift Register has been shifted out and no new data has been written to UDR. This Flag
is especially useful in half-duplex communications interfaces, where a transmitting appli-
cation must enter receive mode and free the communications bus immediately after
completing the transmission.
Bit
$0C ($2C)
Read/Write
Initial Value
Bit
$0B ($2B)
Read/Write
Initial Value
is set).
byte. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal.
selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next
address byte.
Flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a
Framing Error (FE in UCSRA set), since the stop bit is zero. The other slave
MCUs, which still have the MPCM bit set, will ignore the data byte. In this case,
the UDR Register and the RXC or FE Flags will not be affected.
MSB
RXC
R/W
7
0
7
0
r
R/W
TXC
R/W
6
0
6
0
UDRE
R/W
5
0
5
R
0
R/W
FE
R
4
0
4
0
R/W
OR
R
3
0
3
0
R/W
R
2
0
2
–
0
R/W
U2X
R/W
1
0
1
0
MPCM
LSB
R/W
R/W
0
0
0
0
1142E–AVR–02/03
UCSRA
UDR