ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 89

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

Asynchronous Operational
Range
1457G–AVR–09/03
The decision of the logic level of the received bit is taken by doing a majority voting of
the logic value to the three samples in the center of the received bit. The center samples
are emphasized on the figure by having the sample number inside boxes. The majority
voting process is done as follows: If two or all three samples have high levels, the
received bit is registered to be a logic 1. If two or all three samples have low levels, the
received bit is registered to be a logic 0. This majority voting process act as a low pass
filter for the incoming signal on the RxD pin. The recovery process is then repeated until
a complete frame is received. Including the first stop bit. Note that the Receiver only
uses the first stop bit of a frame.
Figure 51 shows the sampling of the stop bit and the earliest possible beginning of the
start bit of the next frame.
Figure 51. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If
the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after
the last of the bits used for majority voting. For normal speed mode, the first low level
sample can be at point marked (A) in Figure 51. For double speed mode the first low
level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-
tion influences the operational range of the Receiver.
The operational range of the Receiver is dependent of the mismatch between the
received bit rate and the internally generated baud rate. If the Transmitter is sending
frames at too fast or too slow bit rates, or the internally generated baud rate of the
Receiver does not have exact base frequency, the Receiver will not be able to synchro-
nize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and
internal Receiver baud rate.
D
S
S
S
(U2X = 0)
(U2X = 1)
Sample
Sample
F
M
RxD
Sum of character size and parity size (D = 5 to 10 bit).
Samples per bit. S = 16 for Normal Speed mode and
S = 8 for Double Speed mode.
First sample number used for majority voting. S
S
Middle sample number used for majority voting. S
S
F
M
R
= 4 for Double Speed mode.
= 5 for Double Speed mode.
slow
=
------------------------------------------ -
S 1
1
1
–
2
D
+
+
D S
3
2
1
S
4
+
S
5
3
F
6
7
4
8
STOP 1
9
5
10
F
(A)
0/1
R
6
= 8 for Normal Speed and
M
fast
= 9 for Normal Speed and
0/1
ATmega323(L)
=
(B)
0/1
0/1
-----------------------------------
D
+
D
1
+
S
2
+
S
S
M
(C)
89