ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet
ATMEGA323-8AI
Specifications of ATMEGA323-8AI
Related parts for ATMEGA323-8AI
ATMEGA323-8AI Summary of contents
Page 1
... Programmable I/O Lines – 40-pin PDIP and 44-lead TQFP • Operating Voltages – 2.7 - 5.5V (ATmega323L) – 4.0 - 5.5V (ATmega323) • Speed Grades – MHz (ATmega323L) – MHz (ATmega323) ® 8-bit Microcontroller 8-bit Microcontroller with 32K Bytes of In-System Programmable Flash ...
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... Pin Configurations ATmega323(L) 2 PDIP (XCK/T0) PB0 1 40 (T1) PB1 2 39 (INT2/AIN0) PB2 3 38 (OC0/AIN1) PB3 4 37 (SS) PB4 5 36 (MOSI) PB5 6 35 (MISO) PB6 7 34 (SCK) PB7 8 33 RESET 9 32 VCC 10 31 GND 11 30 XTAL2 12 29 XTAL1 13 28 (RXD) PD0 14 27 (TXD) PD1 ...
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... Overview The ATmega323 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega323 achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. Block Diagram Figure 1 ...
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... Atmel ATmega323 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega323 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir- cuit Emulators, and evaluation kits. ...
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... The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega323 as listed on page 151. RESET Reset input ...
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... Clock Options Internal RC Oscillator Crystal Oscillator ATmega323(L) 6 The device has the following clock source options, selectable by Flash Fuse bits as shown: Table 1. Device Clocking Options Select Device Clocking Option External Crystal/Ceramic Resonator External Low-frequency Crystal External RC Oscillator Internal RC Oscillator External Clock Note: 1. “ ...
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... For the Timer Oscillator pins, PC6(TOSC1) and PC7(TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768 kHz watch crystal. Applying an external clock source to PC6(TOSC1) is not recommended. 1457G–AVR–09/03 ATmega323( XTAL2 ...
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... The ALU supports arithmetic and logic operations between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 5 shows the ATmega323 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the Register File as well ...
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... Figure 5. The ATmega323 AVR Enhanced RISC Architecture The AVR uses a Harvard architecture concept – with separate memories and buses for Program and Data. The Program memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Pro- gram memory ...
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... ATmega323(L) 10 The 2K bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register ...
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... General Purpose Working Registers register 70 R27 ($1B register 70 R29 ($1D register 70 R31 ($1F) ATmega323(L) 0 Addr. R0 $00 R1 $01 R2 $02 … R13 $0D R14 $0E R15 $0F R16 $10 R17 $11 … R26 $1A X-register Low Byte ...
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... Boot Program section and Application Program section. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATmega323 Program Counter (PC bits wide, thus addressing the 16K Program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail on page 177. See page 197 for a detailed description on Flash data serial downloading using the SPI pins ...
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... Figure 9. SRAM Organization The Program and Data The ATmega323 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory Addressing Modes (SRAM, Register File, and I/O Memory). This section describes the different addressing modes supported by the AVR architecture ...
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... Register Direct, Two Registers Rd and Rr I/O Direct Data Direct ATmega323(L) 14 Figure 11. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 12. I/O Direct Addressing Operand address is contained in 6-bits of the instruction word the destination or source register address ...
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... Figure 16. Data Indirect Addressing With Pre-decrement decrement The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. 1457G–AVR–09/ REGISTER REGISTER REGISTER -1 ATmega323(L) Data Space $0000 $085F Data Space $0000 $085F Data Space $0000 $085F 15 ...
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... Data Indirect with Post- increment Constant Addressing Using the LPM and SPM Instructions Indirect Program Addressing, IJMP and ICALL ATmega323(L) 16 Figure 17. Data Indirect Addressing With Post-increment REGISTER The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing. ...
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... Program execution continues at address The relative address k is from – 2048 to 2047. The EEPROM Data The ATmega323 contains 1K bytes of data EEPROM Memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an Memory endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 66 specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data WR Data RD The I/O space definition of the ATmega323 is shown in Table 2. Table 2. ATmega323 I/O Space I/O Address (SRAM Address) Name $3F ($5F) SREG $3E ($5E) SPH $3D ($5D) SPL ...
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... Table 2. ATmega323 I/O Space (Continued) 1457G–AVR–09/03 I/O Address (SRAM Address) Name Function $33 ($53) TCCR0 Timer/Counter0 Control Register $32 ($52) TCNT0 Timer/Counter0 (8-bit) OSCCAL Oscillator Calibration Register (1) $31 ($51) OCDR On-chip Debug Register $30 ($50) SFIOR Special Function I/O Register $2F ($4F) TCCR1A Timer/Counter1 Control Register A ...
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... OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. All ATmega323 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space ...
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... Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. 1457G–AVR–09/03 SREG at I/O space location $3F ($5F) is defined as: – – Bit $3F ($5F Read/Write R/W R/W R/W Initial Value ATmega323( R/W R/W R/W R/W R SREG 21 ...
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... The Stack Pointer SP – Reset and Interrupt Handling ATmega323(L) 22 The ATmega323 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega323 Data memory has $860 loca- tions, 12 bits are used. Bit $3E ($5E) – – – $3D ($5D) ...
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... Table 4 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. Table 4. Reset and Interrupt Vectors Placement Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega323 is: 1457G–AVR–09/03 (2) Vector No. Program Address ...
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... ATmega323(L) 24 $018 jmp SPI_STC; $01a jmp USART_RXC $01c jmp USART_UDRE ; UDR Empty Handler $01e jmp USART_TXC $020 jmp ADC $022 jmp EE_RDY $024 jmp ANA_COMP $026 jmp TWSI Handler ; $028 MAIN: ldi r16,high(RAMEND); Main program start $029 out SPH,r16 $02a ldi ...
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... When the BOOTRST Fuse is programmed, the boot section size set to 4K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses are: Reset Sources The ATmega323 has five sources of reset: • • • ...
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... ATmega323(L) 26 Figure 24. Reset Logic Power- Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL 100-500k SPIKE Reset Circuit RESET FILTER JTAG Reset Watchdog Register Timer On-chip RC Oscillator Clock Generator CKSEL[3:0] (1) Table 5. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V Power-on Reset POT ...
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... On Power-up, the start-up time is increased with Typ 0.6 ms. 2. “1” means unprogrammed, “0” means programmed. 3. For possible clock selections, see “Clock Options” on page 6. 4. When BODEN is programmed, add 100 µs. 5. When BODEN is programmed, add 25 µs. 6. Default value. ATmega323(L) Start-up Time 4.0V, BODLEVEL Programmed Recommended Usage Ext ...
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... Power-on Reset ATmega323(L) 28 Table 6 shows the start-up times from Reset. When the CPU wakes up from Power- down or Power-save, only the clock counting part of the start-up time is used. The Watchdog Oscillator is used for timing the Real Time part of the start-up time. The num- ber WDT Oscillator cycles used for each time-out is shown in Table 7 ...
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... Period t Figure 27. External Reset During Operation Brown-out Detection ATmega323 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and V value below the trigger level, the Brown-out Reset is immediately activated. When V increases above the trigger level, the Brown-out Reset is deactivated after a delay ...
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... Watchdog Reset MCU Control and Status Register – MCUCSR ATmega323(L) 30 Figure 28. Brown-out Reset During Operation RESET TIME-OUT INTERNAL RESET The hysteresis BOT BOT+ When the Watchdog times out, it will generate a short reset pulse cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out Period t ...
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... Interrupt Flag bit in the GIFR Register before the interrupt is re-enabled. • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the ATmega323 and always reads as zero. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET ...
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... Power-down mode, the user can avoid the three conditions above to ensure that the ref- erence is turned off before entering Power-down mode. The ATmega323 has two 8-bit Interrupt Mask Control Registers: GICR rupt Control Register and TIMSK – Timer/Counter Interrupt Mask Register. ...
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... Interrupts” on page 37. • Bits 4..2 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and always read as zero. • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...
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... If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor- responding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bits 4..0 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and always read as zero. Bit 7 6 ...
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... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register 1457G–AVR–09/03 TIFR. – TIFR. – TIFR. – TIFR. – TIFR. – TIFR. – TIFR. – ATmega323(L) 35 ...
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... The Timer/Counter Interrupt Flag Register – TIFR ATmega323(L) 36 Bit $38 ($58) OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector ...
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... To avoid the MCU entering the sleep mode unless it is the pro- grammers purpose recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. 1457G–AVR–09/03 Bit $37 ($57) SE SM2 SM1 Read/Write R/W R/W R/W Initial Value ATmega323( SM0 ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R/W R ...
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... ATmega323(L) 38 • Bits 6..4 – SM2..0: Sleep Mode Select Bits 2, 1 and 0 These bits select between the six available sleep modes as shown in Table 8. Table 8. Sleep Mode Select SM2 SM1 SM0 Note: 1. Standby mode and Extended Standby mode are only available with external crystals or resonators. • ...
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... Timer/Counter2 interrupts during ADC Noise Reduction mode if the Timer/Counter2 is clocked synchronously. 1457G–AVR–09/03 ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request Any logical change on INT0 generates an interrupt request The falling edge of INT0 generates an interrupt request The rising edge of INT0 generates an interrupt request. ATmega323(L) 39 ...
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... Power-down Mode Power-save Mode Standby Mode Extended Standby Mode ATmega323(L) 40 When the SM2..0 bits are 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external inter- rupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled) ...
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... SFIOR • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and always read as zero. • Bit 3 – ACME: Analog Comparator Multiplexer Enable When this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator ...
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... ATmega323(L) 42 • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is set (one) the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. See “ ...
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... Timer/Counters The ATmega323 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real Time Counter (RTC). Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaler ...
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... ATmega323(L) 44 Figure 31. Prescaler for Timer/Counter2 CK PCK2 Clear XTAL1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named PCK2. PCK2 is by default connected to the main system clock CK. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchro- nously clocked from the PC6(TOSC1) pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC) ...
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... FLOW IRQ MATCH IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR T/C CLEAR TIMER/COUNTER0 T/C CLK SOURCE (TCNT0) UP/DOWN 7 0 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER0 (OCR0) ATmega323(L) T/C0 CONTROL SPECIAL FUNCTIONS REGISTER (TCCR0) IO REGISTER (SFIOR) CK CONTROL LOGIC T0 45 ...
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... ATmega323(L) 46 Figure 33. Timer/Counter2 Block Diagram T/C2 OVER- FLOW IRQ 8-BIT DATA BUS 8-BIT ASYNCH T/C2 DATA BUS TIMER INT. MASK REGISTER (TIMSK T/C CLEAR TIMER/COUNTER2 T/C CLK SOURCE (TCNT2) UP/DOWN 7 0 8-BIT COMPARATOR 7 0 OUTPUT COMPARE REGISTER2 (OCR2) CK PCK2 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK external pin ...
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... Timer/Counter Disconnected from Output Pin OCn 0 1 Toggle the OCn Output Line Clear the OCn Output Line (to Zero Set the OCn Output Line (to One PWM mode, these bits have a different function. Refer to Table 15 for a description ATmega323( COM00 CTC0 CS02 CS01 CS00 R/W R/W R/W ...
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... ATmega323(L) 48 • Bit 3 – CTC0/CTC2: Clear Timer/Counter on Compare Match When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is reset to $00 in the CPU clock cycle following a Compare Match. If the control bit is cleared, the Timer/Counter continues counting and is unaffected by a Compare Match. ...
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... MSB Read/Write R/W R/W R/W Initial Value Bit $3C ($5C) MSB Read/Write R/W R/W R/W Initial Value Bit $23 ($43) MSB Read/Write R/W R/W R/W Initial Value ATmega323( LSB R/W R/W R/W R/W R LSB R/W R/W R/W R/W R LSB R/W R/W ...
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... PWM Modes (Up/Down and Overflow) ATmega323(L) 50 The two different PWM modes are selected by the CTC0 or CTC2 bit in the Timer/Counter Control Registers –TCCR0 or TCCR2 respectively. If CTC0/CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated ...
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... Compare Value changes Synchronized OCn Latch Compare Value changes Unsynchronized OCn Latch Synchronized OCn Latch Unsynchronized OCn Latch (Figure 34 and Figure 35). ATmega323(L) Counter Value Compare Value PWM Output OCn Counter Value Compare Value PWM Output OCn Glitch Compare Value changes ...
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... Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and always read as zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and PC7 are connected to a crystal Oscillator and cannot be used as general I/O pins ...
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... When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a 1457G–AVR–09/03 TCR2UB. 1. Write a value to TCCR2, TCNT2 or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. ATmega323(L) 53 ...
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... Timer/Counter1 ATmega323(L) 54 Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 ...
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... The ICP pin logic is shown in Figure 37. Figure 37. ICP Pin Schematic Diagram If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the Capture Flag. 1457G–AVR–09/03 ATmega323(L) 55 ...
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... Timer/Counter1 Control Register A – TCCR1A ATmega323(L) 56 Bit $2F ($4F) COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin actions affect pin OC1A – Output Compare A ...
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... Input Capture Register – ICR1 – on the rising edge of the Input Capture Pin – ICP. • Bits 5, 4 – Res: Reserved bits These bits are reserved bits in the ATmega323 and always read as zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a Compare A Match ...
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... Timer/Counter1 – TCNT1H and TCNT1L ATmega323(L) 58 When the prescaler is set to divide by 8, the timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C |1,1,1,1,1,1,1,1|... In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter wraps when it reaches the TOP value ...
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... MSB $2A ($4A Read/Write R/W R/W R/W R/W R/W R/W Initial Value Bit $29 ($49) MSB $28 ($48 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega323( LSB R/W R/W R/W R/W R/W R/W R/W R/W R/W R LSB R/W R/W R/W ...
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... Timer/Counter1 Input Capture Register – ICR1H and ICR1L Timer/Counter1 In PWM Mode ATmega323(L) 60 The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. ...
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... Compare Match, up-counting (inverted PWM Not connected Reserved Cleared on Compare Match, set on overflow Set on Compare Match, cleared on overflow ATmega323(L) Timer TOP Value 8-bit $00FF (255) 9-bit $01FF (511) 10-bit $03FF(1023) 8-bit $00FF (255) 9-bit $01FF (511) 10-bit $03FF(1023) Frequency $00FF (255) f /510 ...
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... ATmega323(L) 62 Figure 38. Effects of Unsynchronized OCR1 Latching. Synchronized OC1x Latch Unsynchronized OC1x Latch Note Figure 39. Effects of Unsynchronized OCR1 Latching in Overflow Mode Synchronized OC1x Latch Unsynchronized OC1x Latch Note During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A/B ...
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... Timer/Counter mode, i.e executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 Flags and interrupts. 1457G–AVR–09/03 COM1X1 COM1X0 ATmega323(L) OCR1X Output OC1X $0000 L TOP H $0000 H TOP L 63 ...
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... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled ...
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... WDE even though it is set to one before the disable operation starts. Watchdog. Number of WDT WDP2 WDP1 WDP0 Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles ATmega323(L) Typical Time-out Typical Time-out 0.38 s 0.12 s 0.75 s 0.24 s 1.5 s 0.49 s 3.0 s 0.97 s 6 ...
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... X X • Bits 15..10 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and will always read as zero. • Bits 9..0 – EEAR9..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1,023 ...
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... EECR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled ...
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... Preventing EEPROM Corruption ATmega323(L) 68 The user should poll the EEWE bit before starting the read operation write operation is in progress not possible to set the EERE bit, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 25 lists the typi- cal programming time for EEPROM access from the CPU ...
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... Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega323 and peripheral devices or between several AVR devices. The Interface – SPI ATmega323 SPI includes the following features: • • • • • • • • Figure 41. SPI Block Diagram The interconnection between Master and Slave CPUs with SPI is shown in Figure 42 ...
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... SS Pin Functionality ATmega323(L) 70 Figure 42. SPI Master-Slave Interconnection MSB MASTER LSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in ...
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... Not defined but normally MSB of character just received Not defined but normally LSB of previously transmitted character. Bit $0D ($2D) SPIE SPE DORD Read/Write R/W R/W R/W Initial Value ATmega323(L) (1) ( MSTR CPOL CPHA SPR1 SPR0 R/W R/W R/W R/W R ...
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... The SPI Status Register – SPSR ATmega323(L) 72 • Bit 5 – DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero) ...
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... WCOL set (one), and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega323 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 27) ...
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... USART Overview ATmega323(L) 74 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • ...
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... The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATmega323 USART Pin Table 28 shows the ATmega323 specific USART pin placement. Specification Table 28. ATmega323 Specific USART Pin Placement As XCK is placed on PB0, DDR_XCK in the following refers to DDB0. ...
Page 76
... Clock Generation Internal Clock Generation – The Baud Rate Generator ATmega323(L) 76 The Clock Generation Logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation ...
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... UBRR Contents of the UBRRH and UBRRL Registers 4095) Some examples of UBRR values for some system clock frequency are found in Table 36 (see page 99). depends on the stability of the system clock source therefore recom- osc ATmega323(L) Equation for Calculating (1) Baud Rate UBRR Value f OSC ...
Page 78
... Frame Formats ATmega323(L) 78 Figure 47. Synchronous Mode XCK Timing UCPOL = 0 XCK RxD / TxD UCPOL = 1 XCK RxD / TxD The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 47 shows, when UCPOL is zero the data will be changed at falling XCK edge and sampled at rising XCK edge ...
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... Registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. 1457G–AVR–09/ – odd n 1 – P Parity bit using even parity even P Parity bit using odd parity odd d Data bit n of the character n ATmega323( ...
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... ATmega323(L) 80 (1) Assembly Code Example USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable Receiver and Transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) ...
Page 81
... UDR,r16 ret C Code Example void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE)) ) {}; /* Put data into buffer, sends the data */ UDR = data The example code assumes that the part specific header file is included. ATmega323(L) 81 ...
Page 82
... Sending Frames with 9 Data Bit Transmitter Flags and Interrupts ATmega323( 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low Byte of the character written to UDR. The following code exam- ples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16 ...
Page 83
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register does not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. 1457G–AVR–09/03 ATmega323(L) 83 ...
Page 84
... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega323(L) 84 The USART Receiver is enabled by setting the Receive Enable (RXEN) bit in the UCSRB Register. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. ...
Page 85
... UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the ninth bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl The example code assumes that the part specific header file is included. ATmega323(L) 85 ...
Page 86
... Receive Compete Flag and Interrupt Receiver Error Flags ATmega323(L) 86 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ...
Page 87
... Assembly Code Example USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) C Code Example void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR The example code assumes that the part specific header file is included. ATmega323(L) 87 ...
Page 88
... Reception Asynchronous Clock Recovery Asynchronous Data Recovery ATmega323(L) 88 The USART includes a clock recovery and a data recovery unit for handling asynchro- nous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. ...
Page 89
... Sum of character size and parity size ( bit). Samples per bit for Normal Speed mode and for Double Speed mode. First sample number used for majority voting for Double Speed mode. F Middle sample number used for majority voting for Double Speed mode. M ATmega323(L) STOP 1 (A) ( 0/1 0/1 0 ...
Page 90
... ATmega323( the ratio of the slowest incoming data rate that can be accepted in relation to the slow Receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the Receiver baud rate. Table 30 and Table 31 list the maximum Receiver baud rate error that can be tolerated. ...
Page 91
... MPCM setting. received. The other Slave MCUs, which still have the MPCM bit set, will ignore the data frames. MCU sets the MPCM bit and waits for a new address frame from Master. The process then repeats from 2. ATmega323(L) 91 ...
Page 92
... Accessing UBRRH/UCSRC Registers Write Access ATmega323(L) 92 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written ...
Page 93
... USART_ReadUCSRC( void ) { unsigned char sreg, ucsrc; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; /* Restore Global Interrupt Flag */ SREG = sreg; return ucsrc The example code assumes that the part specific header file is included. ATmega323(L) 93 ...
Page 94
... USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA ATmega323(L) 94 Bit $0C ($2C) Read $0C ($2C) Write Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location ...
Page 95
... Setting this bit enables the Multi-processor Communication mode. When the MPCM bit is set, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 91. 1457G–AVR–09/03 ATmega323(L) 95 ...
Page 96
... USART Control and Status Register B – UCSRB ATmega323(L) 96 Bit $0A ($2A) RXCIE TXCIE UDRIE Read/Write R/W R/W R/W Initial Value • Bit 7 – RXCIE: RX Complete Interrupt Enable Setting this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is set, the Global Interrupt Flag in SREG is set and the RXC bit in UCSRA is set. • ...
Page 97
... Read/Write R/W R/W R/W Initial Value UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation UPM1 UPM0 USBS Stop Bit(s) 0 1-bit 1 2-bit ATmega323( UPM0 USBS UCSZ1 UCSZ0 UCPOL R/W R/W R/W R/W R Parity Mode Disabled (Reserved) Enabled, Even Parity Enabled, Odd Parity 0 UCSRC 0 97 ...
Page 98
... USART Baud Rate Registers – UBRRL and UBRRHs ATmega323(L) 98 • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (character size frame the Receiver and Transmitter uses. Table 35. Character Size ...
Page 99
... Kbps f = 2.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 51 0.2% 103 4800 25 0.2% 51 9600 12 0.2% 25 ATmega323(L) Closest Match – 100% BaudRate 1.8432 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.2% 47 0.0% 95 0.2% 23 0.0% 47 ...
Page 100
... ATmega323(L) 100 Table 36. Examples of UBRR Settings for Commonly Used Oscillator Frequencies – (Continued) UBRR = 0, Error = 0.0% 14.4K 8 -3.5% 16 19.2K 6 -7.0% 12 28.8K 3 8.5% 8 38.4K 2 8.5% 6 57.6K 1 8.5% 3 76.8K 1 -18.6% 2 115.2K 0 8.5% 1 230.4K – – – 250K – – Max 125 Kbps f = 4.0000 MHz ...
Page 101
... UBRR = 0, Error = 0.0% 1457G–AVR–09/03 (Continued) 19.2K 25 0.2% 51 28.8K 16 2.1% 34 38.4K 12 0.2% 25 57.6K 8 -3.5% 16 76.8K 6 -7.0% 12 115.2K 3 8.5% 8 230.4K 1 8.5% 3 250K 1 0.0% 3 0. – – 0 Max 0.5 Mbps 1 Mbps ATmega323(L) 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 101 ...
Page 102
... Two-wire Serial Interface (Byte Oriented) ATmega323(L) 102 The Two-wire Serial Interface supports bi-directional serial communication designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. Various communication configurations can be designed using this bus ...
Page 103
... ADDRESS REGISTER AND COMPARATOR TWAR INPUT DATA SHIFT SDA REGISTER OUTPUT TWDR START/STOP INPUT SCL AND SYNC OUTPUT ARBITRATION SERIAL CLOCK GENERATOR STATUS STATE MACHINE AND STATUS DECODER ATmega323(L) ACK TIMING AND CONTROL CONTROL REGISTER TWCR STATUS REGISTER TWSR 103 ...
Page 104
... The Two-wire Serial Interface Bit Rate Register – TWBR The Two-wire Serial Interface Control Register – TWCR ATmega323(L) 104 Bit $00 ($20) TWBR7 TWBR6 TWBR5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – Two-wire Serial Interface Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a ...
Page 105
... The interface is activated by setting this bit (one). • Bit 1 – Res: Reserved Bit This bit is a reserved bit in the ATmega323 and will always read as zero. • Bit 0 – TWIE: Two-wire Serial Interface Interrupt Enable When this bit is enabled, and the I-bit in SREG is set, the Two-wire Serial Interface inter- rupt will be activated for as long as the TWINT Flag is high ...
Page 106
... Serial Bus. • Bits 2..0 – Res: Reserved bits These bits are reserved in ATmega323 and will always read as zero The TWSR is read only. It contains a status code which reflects the status of the Two- wire Serial Interface logic and the Two-wire Serial Bus. There are 26 possible status codes ...
Page 107
... TWAR, TWDR, and TWSR must have been com- pleted before clearing this flag. 1457G–AVR–09/03 Bit $02 ($22) TWA6 TWA5 TWA4 Read/Write R/W R/W R/W Initial Value Master Transmitter Master Receiver Slave Receiver Slave Transmitter ATmega323( TWA3 TWA2 TWA1 TWA0 TWGCE R/W R/W R/W R/W R TWAR 0 107 ...
Page 108
... Master Transmitter Mode Master Receiver Mode ATmega323(L) 108 When the Two-wire Serial Interface Interrupt Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in Table 37 to Table 44 ...
Page 109
... Assembly code illustrating operation of the Slave Receiver mode is given at the end of the TWI section. 1457G–AVR–09/03 TWAR TWA6 TWA5 TWA4 Value Device’s Own Slave Address TWCR TWINT TWEA TWSTA Value ATmega323(L) TWA3 TWA2 TWA1 TWA0 TWSTO TWWC TWEN – TWGCE TWIE X 109 ...
Page 110
... Slave Transmitter Mode Miscellaneous States ATmega323(L) 110 In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 58). The transfer is initialized as in the Slave Receiver mode. When TWAR and TWCR have been initialized, the Two-wire Serial Interface waits until it is addressed by its own slave address (or the general call address if enabled) followed by the Data Direction bit which must be “ ...
Page 111
... No TWDR action TWDR action TWDR action ATmega323(L) Next Action Taken by Two-wire Serial Interface Hard- TWEA ware X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted; Logic will switch to Master Receiver mode ...
Page 112
... Assembly Code Example – Master Transmitter Mode ATmega323(L) 112 Figure 55. Formats and States in the Master Transmitter Mode MT Successfull S SLA W Transmission to a Slave Receiver $08 Next Transfer Started with a Repeated Start Condition Not Acknowledge Received after the Slave Address Not Acknowledge Received after a Data ...
Page 113
... ACK/NACK has rjmp wait4 ; been received in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MT_DATA_ACK ; different from MT_DATA_ACK ERROR brne ERROR ldi r16, (1<<TWINT) | (1<<TWSTO) | (1<<TWEN) out TWCR, r16 ; Transmit STOP condition ATmega323(L) 113 ...
Page 114
... SLA+R has been transmitted; NOT ACK has been received $50 Data byte has been received; ACK has been returned $58 Data byte has been received; NOT ACK has been returned ATmega323(L) 114 Application Software Response To TWCR To/from TWDR STA STO TWINT Load SLA+R ...
Page 115
... TWCR, r16 ; Clear TWINT bit in TWCR to start transmission ; of SLA+R wait6:in r16,TWCR ; Wait for TWINT Flag set. This indicates that sbrs r16, TWINT ; SLA+R has been transmitted, and ACK/NACK has rjmp wait6 ; been received ATmega323(L) A DATA A P $50 $58 S SLA $10 Other Master ...
Page 116
... ATmega323(L) 116 in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MR_SLA_ACK ; different from MR_SLA_ACK ERROR brne ERROR ldi r16, (1<<TWINT) | (1<<TWEA) | (1<<TWEN) out TWCR, r16 ; Clear TWINT bit in TWCR to start reception of ; data. Setting TWEA causes ACK to be returned ...
Page 117
... Read data byte Read data byte ATmega323(L) Next Action Taken by Two-wire Serial Interface Hard- ware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be ...
Page 118
... Assembly Code Example – Slave Receiver Mode ATmega323(L) 118 Figure 57. Formats and States in the Slave Receiver Mode Reception of the Own S SLA Slave Address and One or more Data Bytes. All are Acknowledged Last Data Byte Received is not Acknowledged Arbitration Lost as Master and Addressed as Slave ...
Page 119
... TWCR, r16 ; Clear TWINT bit in TWCR to start reception of ; data. Setting TWEA causes TWI unit to enter ; not addressed Slave mode with recognition of ; own SLA ;<Wait for next data transmission or do something else> ATmega323(L) 119 ...
Page 120
... ACK has been received $C0 Data byte in TWDR has been transmitted; NOT ACK has been received $C8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATmega323(L) 120 Application Software Response To TWCR To/from TWDR STA STO TWINT Load data byte or X ...
Page 121
... TWINT ; data has been transmitted, and ACK/NACK has rjmp wait15 ; been received in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, ST_DATA_ACK ; different from ST_DATA_ACK ERROR brne ERROR ATmega323(L) DATA A DATA $B8 $C0 A All 1's $C8 Any Number of Data Bytes ...
Page 122
... Hardware $F8 No relevant state information available; TWINT = “0” $00 Bus error due to an illegal START or STOP condition TWI Include File ATmega323(L) 122 ldi r16, 0x44 ; Load data(here, data=0x44)into TWDR Register out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEA) | (1<<TWEN) ...
Page 123
... STOP condition or repeated START condition ;has been received while still addressed as a ;Slave ;***** Miscellaneous States ***** .equ NO_INFO =$F8 ;No relevant state information; TWINT = .equ BUS_ERROR =$00 ;Bus error due to illegal START or STOP ;condition ATmega323(L) “0” ), ACK has been received “0” 123 ...
Page 124
... The Analog Comparator ATmega323(L) 124 The Analog Comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than the voltage on the negative pin PB3 (AIN1), the Analog Comparator Output, ACO, is set (one). The comparator’ ...
Page 125
... To make the comparator trigger the Timer/Counter1 Input Capture Interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). 1457G–AVR–09/03 Bit $08 ($28) ACD ACBG ACO Read/Write R/W R/W R Initial Value 0 0 N/A ATmega323( ACI ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R/W R ...
Page 126
... Analog Comparator Multiplexed Input ATmega323(L) 126 • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter- rupt. The different settings are shown in Table 42. Table 42. ACIS1/ACIS0 Settings ACIS1 ACIS0 ...
Page 127
... The ATmega323 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows each pin of Port used as input for the ADC. The ADC contains a Sample and Hold Amplifier which ensures that the input voltage to the ADC is held at a constant level during conversion ...
Page 128
... Operation ATmega323(L) 128 Figure 60. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL 2.56 V REFERENCE AREF AGND 1.22 V BANDGAP REFERENCE ADC7 ADC6 ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 The ADC converts an analog input voltage to a 10-bit digital value through successive approximation ...
Page 129
... XTAL frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler 1457G–AVR–09/03 Reset ADEN 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE ATmega323(L) 129 ...
Page 130
... ATmega323(L) 130 keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock cycles to initialization and minimize offset errors ...
Page 131
... ADC conversion complete interrupt must be enabled. ADEN = 1 ADSC = 0 ADFR = 0 ADIE = 1 sion once the CPU has been halted. rupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. ATmega323(L) Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 132
... The ADC Multiplexer Selection Register – ADMUX ATmega323(L) 132 Bit $07 ($27) REFS1 REFS0 ADLAR Read/Write R/W R/W R/W Initial Value • Bit 7, 6 – REFS1..0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 22. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set) ...
Page 133
... When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com- plete Interrupt is activated. 1457G–AVR–09/03 MUX4..0 01000..11101 11110 11111 Bit $06 ($26) ADEN ADSC ADFR Read/Write R/W R/W R/W Initial Value ATmega323(L) Single-ended Input Reserved 1.22V ( (AGND ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R/W 0 ...
Page 134
... The ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 ATmega323(L) 134 • Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 47. ADC Prescaler Selections ...
Page 135
... The analog part of the ATmega323 and all analog components in the application 2. Keep analog signal paths as short as possible. Make sure analog tracks run over 3. The AVCC pin on the ATmega323 should be connected to the digital V 4. Use the ADC noise canceler function to reduce induced noise from the CPU. ...
Page 136
... Reference Input Resistance REF V Input Voltage IN R Analog Input Resistance AIN Notes: 1. Values are guidelines only. Actual values are TBD. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V. ATmega323(L) 136 Condition Min Single-ended Conversion REF ADC clock = 200 kHz REF ADC clock = 1 MHz ...
Page 137
... DDA7 DDA6 DDA5 Read/Write R/W R/W R/W Initial Value Bit $19 ($39) PINA7 PINA6 PINA5 Read/Write Initial Value N/A N/A N/A ATmega323( present during Power-down without PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 DDA0 R/W ...
Page 138
... Port A as General Digital I/O Port A Schematics ATmega323(L) 138 All 8-bits in Port A are equal when used as digital I/O pins. PAn, General I/O pin: The DDAn bit in the DDRA Register selects the direction of this pin, if DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin ...
Page 139
... Bit $17 ($37) DDB7 DDB6 DDB5 Read/Write R/W R/W R/W Initial Value Bit $16 ($36) PINB7 PINB6 PINB5 Read/Write Initial Value N/A N/A N/A ATmega323( PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R/W ...
Page 140
... Port B As General Digital I/O Alternate Functions of Port B ATmega323(L) 140 The Port B Input Pins address – PINB – is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. ...
Page 141
... T1, Timer/Counter1 Counter Source. See the timer description for further details. • T0/XCK – Port B, Bit 0 T0, Timer/Counter0 Counter Source. See the timer description for further details. XCK, USART external clock. See the USART description for further details. 1457G–AVR–09/03 ATmega323( present during Power-down without present during CC ...
Page 142
... Port B Schematics ATmega323(L) 142 Note that all port pins are synchronized. The synchronization latches are not shown in the figures. Figure 67. Port B Schematic Diagram (Pin PB0) 1 PB0 0 PUD: PULL-UP DISABLE Figure 68. Port B Schematic Diagram (Pin PB1) PB1 PUD: PULL-UP DISABLE PUD DDB0 ...
Page 143
... WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB PUD: PULL-UP DISABLE ISC2 PB3 PWRDN WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB PUD: PULL-UP DISABLE ATmega323(L) RD RESET DDB2 C WD RESET PORTB2 INT2 CLEAR ...
Page 144
... ATmega323(L) 144 Figure 71. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WP: WRITE PORTB WRITE DDRB WD: RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB MSTR: SPI MASTER ENABLE SPE: SPI ENABLE PUD: PULL-UP DISABLE Figure 72. Port B Schematic Diagram (Pin PB5) MOS ...
Page 145
... PUD: PULL-UP DISABLE MOS PUD PULL- UP PB7 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN READ DDRB RD: SPE: SPI ENABLE MASTER SELECT MSTR PUD: PULL-UP DISABLE ATmega323(L) RD RESET DDB6 C WD RESET PORTB6 MSTR SPE SPI SLAVE OUT SPI MASTER ...
Page 146
... Register – DDRC The Port C Input Pins Address – PINC Port C As General Digital I/O ATmega323(L) 146 Port 8-bit bi-directional I/O port with optional internal pull-ups. Three I/O Memory address locations are allocated for the Port C, one each for the Data Register – ...
Page 147
... JTAG interface. 1457G–AVR–09/03 PUD DDCn PORTCn (in SFIOR) I Input Input Input Output Output 1. n: 7…0, pin number ATmega323(L) (1) Pull-up Comments No Tri-state (Hi-Z) PCn will Source Current if Ext. Pulled Yes Low. No Tri-state (Hi-Z) No Push-pull Zero Output No Push-pull One Output 147 ...
Page 148
... Port C Schematics ATmega323(L) 148 • TCK – Port C, Bit 2 TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter- face is enabled, this pin can not be used as an I/O pin. Refer to the section “JTAG Interface and the On-chip Debug System” on page 157 for details on operation of the JTAG interface. • ...
Page 149
... READ PORTC PIN RD: READ DDRC PUD: PULL-UP DISABLE n: 2..5 PUD MOS PULL- UP PC6 0 1 WP: WRITE PORTC WD: WRITE DDRC RL: READ PORTC LATCH RP: READ PORTC PIN RD: READ DDRC AS2: ASYNCH SELECT T/C2 PUD: PULL-UP DISABLE ATmega323(L) RD RESET DDCn C WD RESET PORTCn RESET DDC6 C WD RESET R ...
Page 150
... ATmega323(L) 150 Figure 78. Port C Schematic Diagram (Pins PC7 WP: WRITE PORTC WD: WRITE DDRC RL: READ PORTC LATCH RP: READ PORTC PIN RD: READ DDRC AS2: ASYNCH SELECT T/C2 PUD: PULL-UP DISABLE PUD 1457G–AVR–09/03 ...
Page 151
... DDD7 DDD6 DDD5 Read/Write R/W R/W R/W Initial Value Bit $10 ($30) PIND7 PIND6 PIND5 Read/Write Initial Value N/A N/A N/A PIND – ATmega323( PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD4 DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R/W ...
Page 152
... Port D As General Digital I/O Alternate Functions of Port D ATmega323(L) 152 PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull up resistor is activated ...
Page 153
... PUD MOS PULL- UP PD0 WP: WRITE PORTD WRITE DDRD WD: RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD RXD: UART RECEIVE DATA RXEN: UART RECEIVE ENABLE PUD: PULL-UP DISABLE ATmega323(L) RD RESET Q D DDD0 C WD RESET Q D PORTD0 RXEN RXD 153 ...
Page 154
... ATmega323(L) 154 Figure 80. Port D Schematic Diagram (Pin PD1) MOS PULL- UP PD1 WP: WRITE PORTD WD: WRITE DDRD READ PORTD LATCH RL: RP: READ PORTD PIN RD: READ DDRD TXD: UART TRANSMIT DATA TXEN: UART TRANSMIT ENABLE PUD: PULL-UP DISABLE Figure 81. Port D Schematic Diagram (Pins PD2 and PD3) ...
Page 155
... RL RP WP: WRITE PORTD 0 WD: WRITE DDRD NOISE CANCELER 1 RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ICNC1 ACIC: COMPARATOR IC ENABLE ACO: COMPARATOR OUTPUT PUD: PULL-UP DISABLE ATmega323(L) RD RESET DDD6 C WD RESET PORTD6 C WP EDGE SELECT ICF1 ICES1 ACIC ACO 155 ...
Page 156
... ATmega323(L) 156 Figure 84. Port D Schematic Diagram (Pin PD7) WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH READ PORTD PIN RP: RD: READ DDRD PUD: PULL-UP DISABLE PUD 1457G–AVR–09/03 ...
Page 157
... Data Memory Break Points on Single Address or Address Range Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface On-chip Debugging Supported by AVR Studio Testing PCBs by using the JTAG Boundary-Scan Capability. Programming the Non-volatile Memories, Fuses and Lock bits. On-chip Debugging. ATmega323(L) ® 157 ...
Page 158
... The Test Access Port – TAP ATmega323(L) 158 The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. • ...
Page 159
... PORT A BOUNDARY SCAN CHAIN JTAG PROGRAMMING INTERFACE INTERNAL FLASH Address SCAN PC MEMORY Data CHAIN Instruction BREAKPOINT UNIT FLOW CONTROL UNIT PERIPHERAL JTAG / AVR CORE COMMUNICATION INTERFACE OCD STATUS AND CONTROL PORT B ATmega323(L) AVR CPU DIGITAL ANALOG PERIPHERIAL UNITS UNITS 159 ...
Page 160
... TAP Controller ATmega323(L) 160 Figure 86. TAP Controller State Diagram 1 Test-Logic-Reset Run-Test/Idle Select-DR Scan 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-Scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 86 depends on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK ...
Page 161
... Program memory Break Points + 2 single Data memory Break Points 2 single Program memory Break Points + 1 Program memory Break Point with mask (‘range Break Point’) 2 single Program memory Break Points + 1 Data memory Break Point with mask (‘range Break Point’) ATmega323(L) 161 ...
Page 162
... JTAG Instructions PRIVATE0; $8 PRIVATE1; $9 PRIVATE2; $A PRIVATE3; $B ATmega323(L) 162 mentation and JTAG instructions are therefore irrelevant for the user of the On-chip Debug system. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addi- tion, the OCDEN Fuse must be programmed and no Lock bits must be set for the On- chip debug system to work ...
Page 163
... EEPROM programming and verifying Fuse programming and verifying Lock bit programming and verifying IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, 1993 Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison- Wesley, 1992 ATmega323(L) 163 ...
Page 164
... IEEE 1149.1 (JTAG) Boundary-Scan Features System Overview ATmega323(L) 164 • JTAG (IEEE std. 1149.1 compliant) Interface • Boundary-Scan Capabilities According to the JTAG Standard • Full Scan of All Port Functions • Supports the Optional IDCODE Instruction • Additional Public AVR_RESET Instruction to Reset the AVR The Boundary-Scan chain has the capability of driving and observing the logic levels on the digital I/O pins ...
Page 165
... Bypass Register Device Identification Register Reset Register Boundary-Scan Chain MSB Bit Device ID Version Part Number 4 bits 16 bits Version JTAG Version number (Binary digits) ATmega323 revision B 0010 Part number ATmega323 ATmega323( Manufacturer ID 11 bits JTAG Part Number (Hex) 0x9501 LSB bit 165 ...
Page 166
... Boundary-Scan Chain Boundary-Scan Specific JTAG Instructions EXTEST; $0 ATmega323(L) 166 The Reset Register is a Test Data Register used to reset the part. Since the AVR tri- states Port Pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. ...
Page 167
... Update-DR: Data from the Boundary-Scan chain is applied to the output latches. However, the output latches are not connected to the pins. Shift-DR: The Reset Register is shifted by the TCK input. Capture-DR: Loads a logic “0” into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted. ATmega323(L) 167 ...
Page 168
... Note: Compatibility issues regarding future devices: Future devices, included replacements for ATmega323 will have Pull-Up Enable signals instead of the Pull-Up Disable signals in the scan path (i.e. inverted logic). The scan cell for the reset signal will have the same logic level as the external pin (i.e. inverted logic). The length of the scan-chain is likely to change in future devices ...
Page 169
... READ DDRX n: 0-7 PUD: PULL-UP DISABLE PuD: JTAG PULL-UP DISABLE OC: JTAG OUTPUT CONTROL OD: JTAG OUTPUT DATA ID: JTAG INPUT DATA The scanned signal is active high, i.e., the RST signal is the inverse of the external RESET pin. ATmega323(L) RD PUD RESET Q D DDXn C WD RESET Q ...
Page 170
... From system pin From previous cell ATmega323 contains a lot of scan chains for internal signals. The description of these signals are not public. However, the user must apply safe values to these cells before applying the Update-DR state of the TAP controller. Note: Incorrect setting of the scan cells for internal signals may cause signal contention and can damage the part ...
Page 171
... General Scan Cell SIG_PRIVATE38 General Scan Cell SIG_PRIVATE39 General Scan Cell SIG_PRIVATE40 General Scan Cell SIG_PRIVATE41 General Scan Cell SIG_PRIVATE42 General Scan Cell SIG_PRIVATE43 Observe Only SIG_PRIVATE44 Observe Only SIG_PRIVATE45 Observe Only SIG_PRIVATE46 Observe Only ATmega323(L) Recommended input when not in use ...
Page 172
... In Figure 89, PXn.Data corresponds to FF0, PXn.Control corresponds to FF1, and PXn. Pullup_dissable corresponds to FF2. Bit and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled Table 58. ATmega323 Boundary-Scan Order Bit Number Signal Name 131 ...
Page 173
... Table 58. ATmega323 Boundary-Scan Order (Continued) 1457G–AVR–09/03 Bit Number Signal Name 104 SIG_PRIVATE27 103 SIG_PRIVATE28 102 SIG_PRIVATE29 101 SIG_PRIVATE30 100 SIG_PRIVATE31 99 SIG_PRIVATE32 98 SIG_PRIVATE33 97 SIG_PRIVATE34 96 SIG_PRIVATE35 95 SIG_PRIVATE36 94 SIG_PRIVATE37 93 SIG_PRIVATE38 92 SIG_PRIVATE39 91 SIG_PRIVATE40 90 SIG_PRIVATE41 89 SIG_PRIVATE42 88 PB0.Data 87 PB0.Control 86 PB0.PuLLup_Disable 85 PB1.Data 84 PB1.Control 83 PB1.PuLLup_Disable 82 PB2.Data 81 PB2.Control 80 PB2 ...
Page 174
... ATmega323(L) 174 Table 58. ATmega323 Boundary-Scan Order (Continued) Bit Number Signal Name 73 PB5.Data 72 PB5.Control 71 PB5.PuLLup_Disable 70 PB6.Data 69 PB6.Control 68 PB6.PuLLup_Disable 67 PB7.Data 66 PB7.Control 65 PB7.PuLLup_Disable 64 RSTT 63 SIG_PRIVATE43 62 SIG_PRIVATE44 61 SIG_PRIVATE45 60 SIG_PRIVATE46 59 PD0.Data 58 PD0.Control 57 PD0.PuLLup_Disable 56 PD1.Data 55 PD1.Control 54 PD1.PuLLup_Disable 53 PD2.Data 52 PD2.Control 51 PD2.PuLLup_Disable 50 PD3.Data 49 PD3.Control 48 PD3.PuLLup_Disable 47 PD4.Data 46 PD4.Control 45 PD4.PuLLup_Disable Module ...
Page 175
... Table 58. ATmega323 Boundary-Scan Order (Continued) 1457G–AVR–09/03 Bit Number Signal Name 44 PD5.Data 43 PD5.Control 42 PD5.PuLLup_Disable 41 PD6.Data 40 PD6.Control 39 PD6.PuLLup_Disable 38 PD7.Data 37 PD7.Control 36 PD7.PuLLup_Disable 35 PC0.Data 34 PC0.Control 33 PC0.PuLLup_Disable 32 PC1.Data 31 PC1.Control 30 PC1.PuLLup_Disable 29 PC6.Data 28 PC6.Control 27 PC6.PuLLup_Disable 26 PC7.Data 25 PC7.Control 24 PC7.PuLLup_Disable 23 PA7.Data 22 PA7.Control 21 PA7.PuLLup_Disable 20 PA6.Data 19 PA6.Control 18 PA6.PuLLup_Disable 17 PA5.Data 16 PA5.Control 15 PA5 ...
Page 176
... PA0.Control 0 PA0.PuLLup_Disable Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-Scan Data Register are included in this description. A BSDL file for ATmega323 is available. Module Port A 1457G–AVR–09/03 ...
Page 177
... Store Program memory (SPM) instruction can only be executed from the Boot Loader Flash section. The program Flash memory in ATmega323 is divided into 256 pages of 64 words each. The Boot Loader Flash section is located at the high address space of the Flash, and can be configured through the BOOTSZ Fuses as shown in Table 59. ...
Page 178
... ATmega323(L) 178 Figure 92. Memory Sections Program Memory Pages BOOTSZ = '11' Application Flash Section 252 (16128 x 16) Boot Flash Section 4 (256 x 16) Program Memory Pages BOOTSZ = '01' Application Flash Section 240 (15360 x 16) Boot Flash Section 16 (1024 x 16) Program Memory Pages BOOTSZ = '10' $0000 Application Flash Section ...
Page 179
... SPMCR. The content of Z6:Z1 is used to address the data in the temporary buffer. Z14:Z7 must point to the page that is supposed to be written. 1457G–AVR–09/03 BOOTRST Reset Address 0 Reset Vector = Application Reset (address $0000) 1 Reset Vector = Boot Loader Reset (see Table 59) ATmega323(L) 179 ...
Page 180
... ATmega323 has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: • ...
Page 181
... LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. 1. “1” means unprogrammed, “0” means programmed Bit BLB12 ATmega323(L) (1) ( BLB11 BLB02 BLB01 ...
Page 182
... EEPROM Write Prevents Writing to SPMCR Addressing the Flash During Self-programming ATmega323(L) 182 It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When ...
Page 183
... In ATmega323, this bit always reads as zero. • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the ATmega323 and always reads as zero. This bit should be written to zero when writing SPMCR. • Bit 4 – ASRE: Application Section Read Enable Before re-entering the application section, the user software must set this bit together with the SPMEN bit and execute SPM within four clock cycles ...
Page 184
... Preventing Flash Corruption ATmega323(L) 184 • Bit 1 – PGERS: Page Erase If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z- pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple- tion of a page erase SPM instruction is executed within four clock cycles ...
Page 185
... SPMCR sbrs temp1, ASB ret ; re-enable the Applicaiton Section ldi spmcrval, (1<<ASRE) + (1<<SPMEN) ATmega323(L) ;PAGESIZEB is page size in BYTES, not words ;use subi for PAGESIZEB<=256 ;restore pointer ;not required for PAGESIZEB<=256 ;restore pointer ;use subi for PAGESIZEB<=256 ...
Page 186
... SPMEN rjmp Wait_spm ret The ATmega323 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 63. The Lock bits can only be erased to “1” with the Chip Erase command. ...
Page 187
... Table 63. Lock Bit Protection Modes Note: Fuse Bits The ATmega323 has 13 Fuse bits, divided in two groups. The Fuse High bits are OCDEN, JTAGEN, SPIEN, EESAVE, BOOTSZ1..0, and BOOTRST, and the Fuse Low bits are BODLEVEL, BODEN, and CKSEL3..0. All Fuses are accessible in Parallel Pro- gramming mode and when programming via the JTAG interface ...
Page 188
... Flash memory) 3. $002: $01 (indicates ATmega323 device when $001 is $95) The ATmega323 has a one byte calibration value for the internal RC Oscillator. This byte resides in the High Byte of address $000 in the signature address space. To make use of this byte, it should be read from this location and written into the normal Flash Program memory by the external programmer ...
Page 189
... Determined by BS1 Load Data (High or Low Data Byte for Flash Determined by BS1 Load Command Action, Idle ATmega323(L) ATmega323 +5V VCC PB7 - PB0 DATA Function 0: Device is Busy Programming, 1: Device is Ready for New Command Output Enable (Active Low) Write Pulse (Active Low) “0” ...
Page 190
... Enter Programming Mode Chip Erase Programming the Flash ATmega323(L) 190 Table 66. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM ...
Page 191
... Figure 95 for signal waveforms Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. ATmega323(L) 191 ...
Page 192
... Programming the EEPROM ATmega323(L) 192 Figure 94. Programming the Flash Waveforms DATA $10 ADDR. LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY +12V RESET OE BS2 PAGEL Figure 95. Programming the Flash Waveforms (continued) DATA DA TA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 The programming algorithm for the EEPROM Data memory is as follows (refer to “Pro- gramming the Flash” ...
Page 193
... Address High Byte needs only be loaded before programming a new 256 byte window in the EEPROM. Skip writing the data value $FF, that is the contents of the entire EEPROM after a Chip Erase. DATA $11 ADDR. HIGH ADDR. LOW XA1 XA2 BS1 XTAL1 WR +12V RESET OE BS2 PAGEL DATA. DATA. ATmega323( LOW 193 ...
Page 194
... Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits ATmega323(L) 194 5. Set OE to “1”. The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 190 for details on Command and Data loading Load Command “ ...
Page 195
... Bit 3 = Boot Lock bit02 Bit 2 = Boot Lock bit01 Bit 1 = Lock bit2 Bit 0 = Lock bit1 DATA. t XLWL t XTAL1 XHXL t t DVXH XLDX Data & Contol t t BVPH PLBX PAGEL t PHPL WR t PLWL RDY/BSY OE t XLOL DATA ATmega323( BVWL RHBX t WLWH WLRL t WLRH t OHDZ t OLDV 195 ...
Page 196
... ATmega323(L) 196 Table 67. Parallel Programming Characteristics, T Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP t Data and Control Valid before XTAL1 High DVXH t XTAL1 Pulse Width High XHXL t Data and Control Hold after XTAL1 Low XLDX t XTAL1 Low to WR Low ...
Page 197
... Low: > 2 CPU clock cycles High: > 2 CPU clock cycles Serial Programming When writing serial data to the ATmega323, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATmega323, data is clocked on the falling edge of SCK. See Figure 99, Figure 100, and Table 70 for timing details. ...
Page 198
... Data Polling Flash Data Polling EEPROM ATmega323(L) 198 3. The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issu- ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable command ...
Page 199
... Includes variation over voltage and temperature after RC Oscillator has been cali- brated to 1.0 MHz 2. Parallel EEPROM programming takes 1K cycles SERIAL DATA INPUT MSB PB5 (MOSI) SERIAL DATA OUTPUT MSB PB6 (MISO) SERIAL CLOCK INPUT PB7(SCK) SAMPLE ATmega323(L) Parallel/Serial Self- Programming programming (1) 2.7V 5. ...
Page 200
... Boot Lock Bit01 Boot Lock Bit02 Boot Lock Bit11 Boot Lock Bit12 CKSEL0 Fuse CKSEL1 Fuse CKSEL2 Fuse CKSEL3 Fuse BODEN Fuse BODLEVEL Fuse BOOTRST Fuse BOOTSZ0 Fuse BOOTSZ1 Fuse EESAVE Fuse JTAGEN Fuse; and I = OCDEN Fuse ATmega323(L) 200 . ...