PIC16F76T-E/SO Microchip Technology, PIC16F76T-E/SO Datasheet - Page 125

• Manufacturer Part Number: PIC16F76T-E/SO
• Description: IC MCU FLASH 8KX14 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F76T-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC16F76TE/SO

1997 Microchip Technology Inc.
The Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all un-masked interrupts or
disables (if cleared) all interrupts. Individual interrupts can be disabled through their correspond-
ing enable bits in the INTCON register. The GIE bit is cleared on reset.
The “return from interrupt” instruction,
bit, which allows any pending interrupt to execute.
The INTCON register contains these interrupts: INT Pin Interrupt, the RB Port Change Interrupt,
and the TMR0 Overflow Interrupt. The INTCON register also contains the Peripheral Interrupt
Enable bit, PEIE. The PEIE bit will enable/disable the peripheral interrupts from vectoring when
the PEIE bit is set/cleared.
When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the
return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt
service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits.
Generally the interrupt flag bit(s) must be cleared in software before re-enabling the global inter-
rupt to avoid recursive interrupts.
Once in the interrupt service routine the source(s) of the interrupt can be determined by polling
the interrupt flag bits. Individual interrupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding
Note 2: When an instruction that clears the GIE bit is executed, any interrupts that were
mask bit or the GIE bit.
pending for execution in the next cycle are ignored. The CPU will execute a NOP in
the cycle immediately following the instruction which clears the GIE bit. The inter-
rupts which were ignored are still pending to be serviced when the GIE bit is set
again.
RETFIE
Section 8. Interrupts
, exits the interrupt routine as well as sets the GIE
DS31008A-page 8-3
8