ATMEGA162L-8MC Atmel, ATMEGA162L-8MC Datasheet - Page 144

• Manufacturer Part Number: ATMEGA162L-8MC
• Description: IC MCU AVR 16K 3V 8MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8MC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Phase Correct PWM Mode
144
ATmega162(V/U/L)
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the
output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal
to MAX will result in a constantly high or low output (depending on the polarity of the out-
put set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The
waveform generated will have a maximum frequency of f
to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM21:0 = 3) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-
slope operation. The counter counts repeatedly from BOTTOM to MAX and then from
MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2)
is cleared on the compare match between TCNT2 and OCR2 while upcounting, and set
on the compare match while downcounting. In inverting output compare mode, the oper-
ation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase
correct PWM mode the counter is incremented until the counter value matches MAX.
When the counter reaches MAX, it changes the count direction. The TCNT2 value will
be equal to MAX for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 65. The TCNT2 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre-
sent compare matches between OCR2 and TCNT2.
Figure 65. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCn
OCn
Period
1
f
OCnPWM
2
=
----------------- -
N 256
f
clk_I/O
oc
3
2 = f
clk_I/O
OCn Interrupt Flag Set
OCRn Update
TOVn Interrupt Flag Set
/2 when OCR2 is set
(COMn1:0 = 2)
(COMn1:0 = 3)
2513C–AVR–09/02