ATMEGA162L-8PC Atmel, ATMEGA162L-8PC Datasheet - Page 129

• Manufacturer Part Number: ATMEGA162L-8PC
• Description: IC MCU AVR 16K 3V 8MHZ 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162L-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timer/Counter1 Control
Register B – TCCR1B
Timer/Counter3 Control
Register B – TCCR3B
2513C–AVR–09/02
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the input capture noise canceler. When the noise can-
celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter
function requires four successive equal valued samples of the ICPn pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a cap-
ture event. When the ICESn bit is written to zero, a falling (negative) edge is used as
trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the
capture.
When a capture is triggered according to the ICESn setting, the counter value is copied
into the Input Capture Register (ICRn). The event will also set the Input Capture Flag
(ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is
enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in
the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently
the input capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit
must be written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ICNC1
ICNC3
R/W
R/W
7
0
7
0
ICES1
ICES3
R/W
R/W
6
0
6
0
R
R
5
–
0
5
–
0
WGM13
WGM33
R/W
R/W
4
0
4
0
WGM12
WGM32
R/W
R/W
3
0
3
0
ATmega162(V/U/L)
CS12
CS32
R/W
R/W
2
0
2
0
CS11
CS31
R/W
R/W
1
0
1
0
CS10
CS30
R/W
R/W
0
0
0
0
TCCR1B
TCCR3B
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