ATMEGA162V-1AC Atmel, ATMEGA162V-1AC Datasheet - Page 145

• Manufacturer Part Number: ATMEGA162V-1AC
• Description: IC MCU AVR 16K 1.8V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-1AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timer/Counter Timing
Diagrams
2513C–AVR–09/02
The Timer/Counter Overflow Flag (
TOM. The interrupt flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM21:0 to three (See Table 63
on page 148). The actual OC2 value will only be visible on the port pin if the data direc-
tion for the port pin is set as output. The PWM waveform is generated by clearing (or
setting) the OC2 Register at the compare match between OCR2 and TCNT2 when the
counter increments, and setting (or clearing) the OC2 Register at compare match
between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
be replaced by the Timer/Counter Oscillator clock. The figures include information on
when interrupt flags are set. Figure 66 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 66. Timer/Counter Timing Diagram, no Prescaling
Figure 67 shows the same timing data, but with the prescaler enabled.
T
TCNTn
(clk
2) is therefore shown as a clock enable signal. In asynchronous mode, clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
MAX - 1
f
OCnPCPWM
TOV2
MAX
) is set each time the counter reaches BOT-
=
----------------- -
N 510
f
clk_I/O
ATmega162(V/U/L)
BOTTOM
BOTTOM + 1
I/O
should
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