ATMEGA162V-1AC Atmel, ATMEGA162V-1AC Datasheet - Page 54

• Manufacturer Part Number: ATMEGA162V-1AC
• Description: IC MCU AVR 16K 1.8V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-1AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Timed Sequences for
Changing the
Configuration of the
Watchdog Timer
Safety Level 0
Safety Level 1
Safety Level 2
54
ATmega162(V/U/L)
The sequence for changing configuration differs slightly between the three safety levels.
Separate procedures are described for each level.
This mode is compatible with the Watchdog operation found in ATmega161. The Watch-
dog Timer is initially disabled, but can be enabled by writing the WDE bit to one without
any restriction. The Time-out period can be changed at any time without restriction. To
disable an enabled Watchdog Timer, the procedure described on page 51 (WDE bit
description) must be followed.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to one without any restriction. A timed sequence is needed when changing the
Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following proce-
dure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
2. Within the next four clock cycles, in the same operation, write the WDE and
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read
as one. A timed sequence is needed when changing the Watchdog Time-out period. To
change the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the
2. Within the next four clock cycles, in the same operation, write the WDP bits as
written to WDE regardless of the previous value of the WDE bit.
WDP bits as desired, but with the WDCE bit cleared.
WDE always is set, the WDE must be written to one to start the timed sequence.
desired, but with the WDCE bit cleared. The value written to the WDE bit is
irrelevant.
2513C–AVR–09/02