PIC18LF2539T-I/SO Microchip Technology, PIC18LF2539T-I/SO Datasheet - Page 146

• Manufacturer Part Number: PIC18LF2539T-I/SO
• Description: IC MCU FLASH 12KX16 EE AD 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2539T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX39
16.4.4
Both 7- and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
16.4.4.1
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is auto-
matically cleared, forcing the SCL output to be held
low. The CKP being cleared to ‘0’ will assert the SCL
line low. The CKP bit must be set in the user’s ISR
before reception is allowed to continue. By holding the
SCL line low, the user has time to service the ISR and
read the contents of the SSPBUF before the master
device can initiate another receive sequence. This will
prevent
Figure 16-13).
16.4.4.2
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address, and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence, as described in 7-bit mode.
DS30485A-page 144
Note:
Note 1: If the user reads the contents of the
2: The CKP bit can be set in software,
buffer
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs, and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a data
sequence, not an address sequence.
CLOCK STRETCHING
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
overruns
from
occurring
(see
Preliminary
16.4.4.3
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs,
regardless of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 16-9).
16.4.4.4
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode, and clock stretching is controlled by the BF flag,
as in 7-bit Slave Transmit mode (see Figure 16-11).
Note 1: If the user loads the contents of SSPBUF,
2: The CKP bit can be set in software,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
regardless of the state of the BF bit.
Clock Stretching for 7-bit Slave
Transmit Mode
Clock Stretching for 10-bit Slave
Transmit Mode
 2002 Microchip Technology Inc.