AT91RM9200-QI-002 SL383 Atmel, AT91RM9200-QI-002 SL383 Datasheet - Page 20

• Manufacturer Part Number: AT91RM9200-QI-002 SL383
• Description: IC ARM MCU 16BIT 128K 208PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QI-002 SL383

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT91RM9200QI002SL

9.4
9.5
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Debug Unit
PIO Controller
AT91RM9200
• Four operating modes:
• System peripheral to facilitate debug of Atmel’s ARM-based systems
• Composed of the following functions
• Two-pin UART
• Debug Communication Channel Support
• Chip ID Registers
• Up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– the Master Clock MCK
– the USB Clocks, UHPCK and UDPCK, respectively for the USB Host Port and the
– Programmable automatic PLL switch-off in USB Device suspend conditions
– up to thirty peripheral clocks
– four programmable clock outputs PCK0 to PCK3
– Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode
– Two-pin UART
– Debug Communication Channel (DCC) support
– Chip ID Registers
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Interrupt generation
– Support for two PDC channels with connection to receiver and transmitter
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Interrupt generation
– Identification of the device revision, sizes of the embedded memories, set of
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
USB Device Port
Generator
peripherals
1768MS–ATARM–09-Jul-09