ATMEGA88V-10AU Atmel, ATMEGA88V-10AU Datasheet - Page 35

• Manufacturer Part Number: ATMEGA88V-10AU
• Description: IC AVR MCU 8K 10MHZ 1.8V 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88V-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire, SPI, USART, Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3 bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.10
8.11
2545S–AVR–07/10
Timer/Counter Oscillator
System Clock Prescaler
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-
nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with
XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an
internal RC Oscillator is selected as system clock source. See
connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to
logic one. See
on selecting external clock as input instead of a 32 kHz crystal.
The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by
setting the
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clk
divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
CLKPR to zero.
“CLKPR – Clock Prescale Register” on page
“Asynchronous Operation of Timer/Counter2” on page 150
Table 8-14 on page
37.
I/O
36. This feature can be used to
ATmega48/88/168
, clk
Figure 8-2 on page 29
ADC
, clk
CPU
for further description
, and clk
for crystal
FLASH
are
35