AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 123

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

4341H–MP3–10/07
Table 16-4.
Reset Value = 0000 0000b
Table 16-5.
Reset Value = 0000 0000b
Bit Number
Bit Number
FEN
6 - 0
7 - 6
2 - 1
7
7
7
5
4
3
0
-
Mnemonic
Mnemonic
WUPCPU
UADD6:0
EORINT
USBADDR Register
USBADDR (S:C6h) – USB Address Register
USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
SOFINT
UADD6
SPINT
FEN
Bit
Bit
6
6
-
-
-
Description
Function Enable Bit
Set to enable the function. The device firmware should set this bit after it has received a
USB reset and participate in the following configuration process with the default address
(FEN is reset to 0).
Cleared by hardware at power-up, should not be cleared by the device firmware once
set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the value set by a SET_ADDRESS request received by the
device firmware.
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated by a
non-idle signal from USB line (not by an upstream resume). This triggers a USB interrupt
when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when an USB Start of Frame packet (SOF) has been properly received.
This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
Reserved
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for 3
ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
Cleared by software.
WUPCPU
UADD5
5
5
EORINT
UADD4
4
4
SOFINT
UADD3
AT8xC51SND2C/MP3B
3
3
UADD2
2
2
-
UADD1
1
1
-
UADD0
SPINT
0
0
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