AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 238

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

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AT8xC51SND2C/MP3B
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10. Power Management ............................................................................... 47
Description ............................................................................................... 2
Typical Applications ................................................................................ 2
Block Diagram .......................................................................................... 3
Pin Description ......................................................................................... 4
Clock Controller ..................................................................................... 13
Program/Code Memory ......................................................................... 18
Data Memory .......................................................................................... 24
Special Function Registers ................................................................... 31
Interrupt System .................................................................................... 37
4.1 Pinouts ..................................................................................................................... 4
4.2 ................................................................................................................................. 5
4.3 Signals...................................................................................................................... 6
4.4 Internal Pin Structure.............................................................................................. 12
5.1 Oscillator ................................................................................................................ 13
5.2 X2 Feature.............................................................................................................. 14
5.3 PLL ......................................................................................................................... 14
5.4 Registers ................................................................................................................ 16
6.1 ROM Memory Architecture ..................................................................................... 19
6.2 Flash Memory Architecture .................................................................................... 19
6.3 Hardware Security System ..................................................................................... 20
6.4 Boot Memory Execution ......................................................................................... 20
6.5 Preventing Flash Corruption................................................................................... 21
6.6 Registers ................................................................................................................ 22
6.7 Hardware Bytes ...................................................................................................... 22
7.1 Internal Space ........................................................................................................ 24
7.2 External Space ....................................................................................................... 25
7.3 Dual Data Pointer ................................................................................................... 27
7.4 Registers ................................................................................................................ 29
9.1 Interrupt System Priorities ...................................................................................... 37
9.2 External Interrupts .................................................................................................. 40
9.3 Registers ................................................................................................................ 41
10.1 Reset .................................................................................................................... 47
4341H–MP3–10/07