AT89S8253-24JC Atmel, AT89S8253-24JC Datasheet - Page 30

• Manufacturer Part Number: AT89S8253-24JC
• Description: IC 8051 MCU FLASH 12K 44PLCC
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24JC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

Figure 14-8. SPI Transfer Format with CPHA = 0
Note:
Figure 14-9. SPI Transfer Format with CPHA = 1
Note:
15. Interrupts
30
*Not defined but normally MSB of character just received
*Not defined but normally LSB of previously transmitted character
AT89S8253
(FOR REFERENCE)
(FROM MASTER)
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
(FROM SLAVE)
SCK CYCLE #
The AT89S8253 has a total of six interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all
shown in
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that
write a 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The serial interrupt is the logical OR of bits RI and TI in register SCON and also bit SPIF in
SPSR (if SPIE in SPCR is set). None of these flags is cleared by hardware when the service rou-
tine is vectored to. The service routine may have to determine whether the UART or SPI
generated the interrupt.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
MOSI
MISO
Figure
Table 15-1
*
15-1.
MSB
MSB
1
shows that bit position IE.6 is unimplemented. User software should not
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
8
LSB
LSB
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