AT89C51SND1C-ROTUL Atmel, AT89C51SND1C-ROTUL Datasheet - Page 14

• Manufacturer Part Number: AT89C51SND1C-ROTUL
• Description: IC 8051 MCU FLASH 64K MP3 80TQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3
5.3.1
14
PLL
AT8xC51SND1C
PLL Description
is the oscillator frequency.
Note:
Figure 5-3.
Note:
The AT8xC51SND1C PLL is used to generate internal high frequency clock (the PLL Clock) syn-
chronized with an external low-frequency (the Oscillator Clock). The PLL clock provides the MP3
decoder, the audio interface, and the USB interface clocks. Figure 5-4 shows the internal struc-
ture of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock com-
ing from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Table 17) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-
ing or extracting charges from the external filter connected on PFILT pin (see Figure 5-5). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
charge pump. It generates a square wave signal: the PLL clock.
1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see
1. In order to prevent any incorrect operation while operating in X2 mode, user must be aware
X1 ÷ 2
X2 Bit
Clock
page
or X2 mode depending on the X2B value. Using AT83SND1C (ROM Version) the system
always boots in standard mode. X2B bit can be changed to X2 mode later by software.
that all peripherals using clock frequency as time reference (timers, etc.) will have their time
reference divided by 2. For example, a free running timer generating an interrupt every 20 ms
will then generate an interrupt every 10 ms.
X1
Mode Switching Waveforms
24). Using the AT89C51SND1C (Flash Version) the system can boot either in standard
STD Mode
X2 Mode
(1)
ref
produced by the
STD Mode
4109L–8051–02/08
Table 23 on