ATMEGA649V-8AI Atmel, ATMEGA649V-8AI Datasheet - Page 166

• Manufacturer Part Number: ATMEGA649V-8AI
• Description: IC AVR MCU FLASH 64K 1.8V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649V-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

166
ATmega329/3290/649/6490
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 18-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 18-4.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 18-5.
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
0
1
0
1
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
Figure 18-3
SPR1
0
0
1
1
0
0
1
1
and
Leading Edge
Leading Edge
Figure 18-4
Figure 18-3
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
for an example. The CPOL functionality is sum-
and
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
Figure 18-4
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
Trailing Edge
Trailing Edge
for an example. The CPOL
Sample
Falling
Rising
Setup
2552K–AVR–04/11
osc
is