MCU AVR 32K FLASH 28-PDIP

ATMEGA328P-PU

Manufacturer Part NumberATMEGA328P-PU
DescriptionMCU AVR 32K FLASH 28-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA328P-PU datasheets
 


Specifications of ATMEGA328P-PU

Core ProcessorAVRCore Size8-Bit
Speed20MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o23
Program Memory Size32KB (16K x 16)Program Memory TypeFLASH
Eeprom Size1K x 8Ram Size2K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 VData ConvertersA/D 6x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case28-DIP (0.300", 7.62mm)Processor SeriesATMEGA32x
CoreAVR8Data Bus Width8 bit
Data Ram Size2 KBInterface Type2-Wire, SPI, USART
Maximum Clock Frequency20 MHzNumber Of Programmable I/os23
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc10 bit, 6 ChannelCpu FamilyATmega
Device CoreAVRDevice Core Size8b
Frequency (max)20MHzTotal Internal Ram Size2KB
# I/os (max)23Number Of Timers - General Purpose3
Operating Supply Voltage (typ)2.5/3.3/5VOperating Supply Voltage (max)5.5V
Operating Supply Voltage (min)1.8VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingThrough HolePin Count28
Package TypePDIPData Rom Size1 KB
A/d Bit Size10 bitA/d Channels Available6
Height4.57 mmLength34.8 mm
Supply Voltage (max)5.5 VSupply Voltage (min)1.8 V
Width7.49 mmController Family/seriesAVR MEGA
No. Of I/o's23Eeprom Memory Size1KB
Ram Memory Size2KBCpu Speed20MHz
Rohs CompliantYesFor Use WithATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Download datasheet (23Mb)Embed
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Features
High Performance, Low Power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
– 4/8/16/32K Bytes of In-System Self-Programmable Flash program memory
– 256/512/512/1K Bytes EEPROM
– 512/1K/1K/2K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V
Temperature Range:
°
°
– -40
C to 85
C
Speed Grade:
– 0 - 4 MHz@1.8 - 5.5V, 0 - 10 MHz@2.7 - 5.5.V, 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active Mode: 0.2 mA
– Power-down Mode: 0.1 µA
– Power-save Mode: 0.75 µA (Including 32 kHz RTC)
®
8-Bit Microcontroller
(1)
2
C compatible)
8-bit
Microcontroller
with 4/8/16/32K
Bytes In-System
Programmable
Flash
ATmega48A
ATmega48PA
ATmega88A
ATmega88PA
ATmega168A
ATmega168PA
ATmega328
ATmega328P
Rev. 8271C–AVR–08/10

ATMEGA328P-PU Summary of contents

  • Page 1

    ... Active Mode: 0.2 mA – Power-down Mode: 0.1 µA – Power-save Mode: 0.75 µA (Including 32 kHz RTC) ® 8-Bit Microcontroller ( compatible) 8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash ATmega48A ATmega48PA ATmega88A ATmega88PA ATmega168A ATmega168PA ATmega328 ATmega328P Rev. 8271C–AVR–08/10 ...

  • Page 2

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 1. Pin Configurations Figure 1-1. Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5 NOTE: Bottom pad should be soldered to ground. ...

  • Page 3

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical ...

  • Page 4

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The various special features of Port D are elaborated in 89. 1.1 the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally CC connected to V through a low-pass filter. ...

  • Page 5

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 2. Overview The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a low-power CMOS 8-bit microcon- troller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P achieves through- puts approaching 1 MIPS per MHz allowing the ...

  • Page 6

    ... Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com- bined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip Boot pro- gram running on the AVR core ...

  • Page 7

    ... Table 2-1. Device ATmega168PA ATmega328 ATmega328P ATmega48A/48PA/88A/88PA/168A/168PA/328/328P support a real Read-While-Write Self-Pro- gramming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...

  • Page 8

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6. AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...

  • Page 9

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as ...

  • Page 10

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine ...

  • Page 11

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit ...

  • Page 12

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.4.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, ...

  • Page 13

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU ...

  • Page 14

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 6.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must ...

  • Page 15

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= ...

  • Page 16

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 7. AVR Memories 7.1 Overview ATmega48A/48PA/88A/88PA/168A/168PA/328/328P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P features an EEPROM Memory for data storage. All three ...

  • Page 17

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 7-1. Figure 7-2. 8271C–AVR–08/10 Program Memory Map ATmega 48A/48PA Program Memory Application Flash Section Program Memory Map ATmega88A, ATmega88PA, ATmega168A, ATmega168PA, ATmega328 and ATmega328P Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF/0x3FFF 17 ...

  • Page 18

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 7.3 SRAM Data Memory Figure 7-3 is organized. The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended ...

  • Page 19

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 7.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 7-4. 7.4 EEPROM Data Memory The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P contains 256/512/512/1K bytes of ...

  • Page 20

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 7.4.2 Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be ...

  • Page 21

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 7.5.1 General Purpose I/O Registers The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly use- ful for storing global variables and Status Flags. General Purpose I/O Registers ...

  • Page 22

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE possible to program data in one atomic ...

  • Page 23

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR ...

  • Page 24

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData 8271C–AVR–08/10 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 ...

  • Page 25

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example ...

  • Page 26

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...

  • Page 27

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8.1.3 Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 8.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the ...

  • Page 28

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 selectable delays are shown in dependent as shown in Table 8-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual ...

  • Page 29

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 8-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3...1 as shown in on page Table 8-3. Frequency Range Notes: ...

  • Page 30

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 8-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 8.4 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting ...

  • Page 31

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 8-3. Table 8-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, ...

  • Page 32

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8.5 Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified ...

  • Page 33

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 8-9. SUT1... Table 8-10. CKSEL3... 0 0100 0101 Note: 8.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be ...

  • Page 34

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-12. Table 8-12. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 8.7 128 kHz Internal Oscillator The 128 kHz ...

  • Page 35

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 8-4. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8-16. Table 8-16. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock, it ...

  • Page 36

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source. Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. ...

  • Page 37

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 8.12 Register Description 8.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations ...

  • Page 38

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 ...

  • Page 39

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the ...

  • Page 40

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (1) 9.2 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see 298 and onwards, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to ...

  • Page 41

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.5 Power-down Mode When the SM2...0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface address ...

  • Page 42

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.8 Extended Standby Mode When the SM2...0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that the ...

  • Page 43

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.10.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will ...

  • Page 44

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.11 Register Description 9.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits [7:4]: Reserved These bits are unused in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and ...

  • Page 45

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 9.11.2 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see on page ...

  • Page 46

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI ...

  • Page 47

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For ATmega168A/168PA/328/328P the instruction placed at the Reset Vector must ...

  • Page 48

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 10-1. Reset Logic BODLEVEL [2..0] RSTDISBL 10.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be ...

  • Page 49

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock ...

  • Page 50

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 10-5. Brown-out Reset During Operation 10.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting ...

  • Page 51

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 10.8 Watchdog Timer 10.8.1 Features • Clocked from separate ...

  • Page 52

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera- tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows ...

  • Page 53

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay ...

  • Page 54

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset ...

  • Page 55

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 10.9 Register Description 10.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 7:4: Reserved These bits are unused bits in ...

  • Page 56

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To ...

  • Page 57

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 10-2. WDP3 8271C–AVR–08/10 Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 256K (262144) cycles 512K (524288) cycles 0 0 ...

  • Page 58

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 11. Interrupts ...

  • Page 59

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-1. Reset and Interrupt Vectors in ATmega48A and ATmega48PA (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega 48A/48PA is: ...

  • Page 60

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 11.2 Interrupt Vectors in ATmega88A and ATmega88PA Table 11-2. Reset and Interrupt Vectors in ATmega88A and ATmega88PA Program (2) Vector No. Address (1) 1 0x000 2 0x001 3 0x002 4 0x003 5 0x004 6 0x005 7 0x006 8 0x007 ...

  • Page 61

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88A/88PA is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E ...

  • Page 62

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset ...

  • Page 63

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 11.3 Interrupt Vectors in ATmega168A and ATmega168PA Table 11-4. Reset and Interrupt Vectors in ATmega168A and ATmega168PA Program (2) VectorNo. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A ...

  • Page 64

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 11-5 on page 64 tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the ...

  • Page 65

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x0034 0x0035 0x0036 0x0037 0x0038 ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and ...

  • Page 66

    ... ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Address Labels Code ; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C32 ; 0x1C33 0x1C34 0x1C35 0x1C36 0x1C37 0x1C38 11.4 Interrupt Vectors in ATmega328 and ATmega328P Table 11-6. Reset and Interrupt Vectors in ATmega328 and ATmega328P Program (2) VectorNo. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A 7 ...

  • Page 67

    ... EEPROM Ready ANALOG COMP Analog Comparator TWI 2-wire Serial Interface SPM READY Store Program Memory Ready 279. shows reset and Interrupt Vectors placement for the various combina- Reset and Interrupt Vectors Placement in ATmega328 and ATmega328P IVSEL Reset Address 1 0 0x000 1 1 0x000 ...

  • Page 68

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 ; 0x0033RESET: 0x0034 0x0035 0x0036 0x0037 0x0038 ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit ...

  • Page 69

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ; .org 0x3C00 0x3C00 0x3C01 0x3C02 0x3C03 0x3C04 0x3C05 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the ...

  • Page 70

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are ...

  • Page 71

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 12. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured ...

  • Page 72

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 12.2 Register Description 12.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused bits ...

  • Page 73

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 12.2.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 1 – INT1: External Interrupt ...

  • Page 74

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 12.2.4 PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will always read as zero. • Bit 2 – PCIE2: Pin Change ...

  • Page 75

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set ...

  • Page 76

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

  • Page 77

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ...

  • Page 78

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port ...

  • Page 79

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when ...

  • Page 80

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, ...

  • Page 81

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin ...

  • Page 82

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-2 ure 13-5 on page 81 generated internally in the modules having the alternate function. Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions ...

  • Page 83

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port ...

  • Page 84

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis- connected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to ...

  • Page 85

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source. • ICP1/CLKO/PCINT0 – Port ...

  • Page 86

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-6. Port Pin 8271C–AVR–08/10 Overriding Signals for Alternate ...

  • Page 87

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on ...

  • Page 88

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an ...

  • Page 89

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-9. Port Pin 8271C–AVR–08/10 Overriding Signals for Alternate ...

  • Page 90

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering ...

  • Page 91

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • INT0/PCINT18 – Port D, Bit 2 INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source. • ...

  • Page 92

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 13-11. Overriding Signals for Alternate Functions in PD3...PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8271C–AVR–08/10 PD3/OC2B/INT1/ PD2/INT0/ PCINT19 PCINT18 OC2B ENABLE 0 OC2B 0 ...

  • Page 93

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.4 Register Description 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Notes: • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even ...

  • Page 94

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 13.4.8 PORTD – The Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 13.4.9 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 13.4.10 PIND – The Port D Input Pins Address Bit ...

  • Page 95

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14. 8-bit Timer/Counter0 with PWM 14.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM ...

  • Page 96

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-1. 8-bit Timer/Counter Block Diagram 14.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the ...

  • Page 97

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. ...

  • Page 98

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how ...

  • Page 99

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis- abled the CPU will access the ...

  • Page 100

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- ...

  • Page 101

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its ...

  • Page 102

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the pin is set to output. The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents ...

  • Page 103

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 ...

  • Page 104

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter ...

  • Page 105

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the ...

  • Page 106

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 14-11 PWM mode where OCR0A is TOP. Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk ...

  • Page 107

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.9 Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both ...

  • Page 108

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 14-4 rect PWM mode. Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 ...

  • Page 109

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 14-7 rect PWM mode. Table 14-7. COM0B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform ...

  • Page 110

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.9.2 TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring ...

  • Page 111

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 14-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This ...

  • Page 112

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 14.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare ...

  • Page 113

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an ...

  • Page 114

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15. 16-bit Timer/Counter1 with PWM 15.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear ...

  • Page 115

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures ...

  • Page 116

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 put Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input ...

  • Page 117

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two ...

  • Page 118

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write ...

  • Page 119

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example TIM16_WriteTCNT1: C Code Example void TIM16_WriteTCNT1( unsigned int Note: The assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to TCNT1. 15.3.1 Reusing the Temporary ...

  • Page 120

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is ...

  • Page 121

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that ...

  • Page 122

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is ...

  • Page 123

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously ...

  • Page 124

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x ...

  • Page 125

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the ...

  • Page 126

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 non-PWM modes refer to page 136, and for phase correct and phase and frequency correct PWM refer to page 136. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are ...

  • Page 127

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to ...

  • Page 128

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is ...

  • Page 129

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the ...

  • Page 130

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter ...

  • Page 131

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the ...

  • Page 132

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches ...

  • Page 133

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is ...

  • Page 134

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 15-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 ...

  • Page 135

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 15-13 Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A ...

  • Page 136

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 15-2 PWM mode. Table 15-2. COM1A1/COM1B1 Note: Table 15-3 correct or the phase and frequency correct, PWM mode. Table 15-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the ...

  • Page 137

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 15-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

  • Page 138

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – ...

  • Page 139

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ...

  • Page 140

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This ...

  • Page 141

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP ...

  • Page 142

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 16. Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 95 114 share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Internal Clock ...

  • Page 143

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of ...

  • Page 144

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 16.4 Register Description 16.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the ...

  • Page 145

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 17.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow ...

  • Page 146

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the ...

  • Page 147

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock ...

  • Page 148

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is ...

  • Page 149

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit ...

  • Page 150

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x ...

  • Page 151

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can ...

  • Page 152

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram ...

  • Page 153

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 generated will have a maximum frequency of f ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.7.4 Phase Correct PWM ...

  • Page 154

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction ...

  • Page 155

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 17-10 Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, ...

  • Page 156

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for ...

  • Page 157

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that ...

  • Page 158

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized ...

  • Page 159

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of ...

  • Page 160

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 17-4 rect PWM mode. Table 17-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 ...

  • Page 161

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Note: Table 17-7 rect PWM mode. Table 17-7. COM2B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P and will always read as zero. • Bits 1:0 – WGM21:0: ...

  • Page 162

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11.2 TCCR2B – Timer/Counter Control Register B Bit (0xB1) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...

  • Page 163

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 17-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This ...

  • Page 164

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register ...

  • Page 165

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 17.11.8 ASSR – Asynchronous Status Register Bit (0xB6) Read/Write Initial Value • Bit 7 – Reserved This bit is reserved and will always read as zero. • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written ...

  • Page 166

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 17.11.9 GTCCR ...

  • Page 167

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18. SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • ...

  • Page 168

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 18-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in 169. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when ...

  • Page 169

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 18-2. SPI Master-slave Interconnection ...

  • Page 170

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8271C–AVR–08/10 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set ...

  • Page 171

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8271C–AVR–08/10 (1) ...

  • Page 172

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.3 SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured ...

  • Page 173

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 8271C–AVR–08/10 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE ...

  • Page 174

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.5 Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register ...

  • Page 175

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship ...

  • Page 176

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 18.5.3 SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data ...

  • Page 177

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19. USART0 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, ...

  • Page 178

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 19-1. USART Block Diagram Note: 19.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and ...

  • Page 179

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Figure 19-2 Figure 19-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of ...

  • Page 180

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 19-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD ...

  • Page 181

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of ...

  • Page 182

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is ...

  • Page 183

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the ...

  • Page 184

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { ... ... } void USART_Init( unsigned int ubrr Note: More advanced initialization routines ...

  • Page 185

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 19.6.1 Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the ...

  • Page 186

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling ...

  • Page 187

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the ...

  • Page 188

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning ...

  • Page 189

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: 8271C–AVR–08/10 (1) ; Wait for data to be received in r16, UCSRnA sbrs r16, RXCn rjmp USART_Receive ; Get status and 9th bit, ...

  • Page 190

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as ...

  • Page 191

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data ...

  • Page 192

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.8.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal ...

  • Page 193

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 19-7 on page 193 of the start bit of ...

  • Page 194

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-2 on page 194 that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 19-2. # (Data+Parity Bit) Table 19-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate ...

  • Page 195

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 setting, but has to be used differently when part of a system utilizing the Multi-processor Communication mode. If the Receiver is set up to receive frames that contain data bits, then the first ...

  • Page 196

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see Range” on page Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f ...

  • Page 197

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 ...

  • Page 198

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 ...

  • Page 199

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 ...

  • Page 200

    ATmega48A/48PA/88A/88PA/168A/168PA/328/328 19.11 Register Description 19.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or ...