W78E051C40DL Nuvoton Technology Corporation of America, W78E051C40DL Datasheet - Page 5

• Manufacturer Part Number: W78E051C40DL
• Description: IC MCU 8-BIT 4K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E051C40DL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5. FUNCTIONAL DESCRIPTION
The W78E051C architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
5.1 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
INT2 / INT3
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
INTERRUPT SOURCE
PX3
EX3
ADDRESS
VECTOR
IE3
0BH
1BH
03H
13H
23H
33H
3BH
SEQUENCE WITHIN
IT3
PRIORITY LEVEL
0 (highest)
6 (lowest)
POLLING
- 5 -
1
2
3
4
5
PX2
Publication Release Date: November 10, 2006
W78E51C/W78E051C
REQUIRED
SETTINGS
EX2
XICON.2
XICON.6
ENABLE
IE.0
IE.1
IE.2
IE.3
IE.4
IE2
INTERRUPT TYPE
EDGE/LEVEL
XICON.0
XICON.3
TCON.0
TCON.2
Revision A4
-
-
-
IT2