W78E516B40DL Nuvoton Technology Corporation of America, W78E516B40DL Datasheet - Page 14

• Manufacturer Part Number: W78E516B40DL
• Description: IC MCU 8-BIT 64K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E516B40DL

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5.12 In-System Programming (ISP) Mode
The W78E516B equips one 64K byte of main Flash EPROM bank for application program (called
APROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LDROM). In the
normal operation, the microcontroller executes the code in the APROM. If the content of APROM
needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode
by setting the CHPCON register. The CHPCON is read-only by default, software must write two
specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write
attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON
register write attribute. The W78E516B achieves all in-system programming operations including
enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit
CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode.
Because device needs proper time to complete the ISP operations before awaken from idle mode,
software may use timer interrupt to control the duration for device wake-up from idle mode. To perform
ISP operation for revising contents of APROM, software located at APROM setting the CHPCON
register then enter idle mode, after awaken from idle mode the device executes the corresponding
interrupt service routine in LDROM. Because the device will clear the program counter while switching
from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to
00H at LDROM area. The device offers a software reset for switching back to APROM while the
content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1
will result a software reset to reset the CPU. The software reset serves as a external reset. This in-
system programming feature makes the job easy and efficient in which the application needs to
update firmware frequently. In some applications, the in-system programming feature make it possible
to easily update the system firmware without opening the chassis.
REGISTER
P4xAL
P4xAH
ADDRESS BUS
WRITE
READ
P4 REGISTER
P4.x
REGISTER
P4xCMP0
P4xCMP1
EQUAL
Bit Length
Selectable
comparator
P4xCSINV
- 14 -
P4xFUN0
P4xFUN1
P4.x INPUT DATA BUS
DATA I/O
RD/WR_CS
WR_CS
RD_CS
MUX 4->1
P4.x
PIN
W78E516B