C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet
C8051F330
Specifications of C8051F330
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C8051F330 Summary of contents
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... HIGH-SPEED CONTROLLER CORE 8KB 8051 CPU (25MIPS) DEBUG CIRCUITRY Copyright © 2004 by Silicon Laboratories 8 kB ISP Flash MCU Family 24.5 MHz with ±2% accuracy supports crystal-less UART operation 80/40/20/10 kHz low frequency, low power Port 0 Port 1 P2.0 768 B SRAM POR WDT C8051F330/1, C8051F330D ...
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... C8051F330/1, C8051F330D 2 Rev. 1.2 ...
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... Settling Time Requirements ..................................................................... 40 5.4. Programmable Window Detector ...................................................................... 45 5.4.1. Window Detector In Single-Ended Mode ................................................. 47 5.4.2. Window Detector In Differential Mode...................................................... 48 6. 10-Bit Current Mode DAC (IDA0, C8051F330 and C8051F330D only)................ 51 6.1. IDA0 Output Scheduling ................................................................................... 51 6.1.1. Update Output On-Demand ..................................................................... 51 6.1.2. Update Output Based on Timer Overflow ................................................ 52 6 ...
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... C8051F330/1, C8051F330D 9.2.5. Stack ....................................................................................................... 72 9.2.6. Special Function Registers....................................................................... 73 9.2.7. Register Descriptions ............................................................................... 76 9.3. Interrupt Handler ............................................................................................... 79 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 79 9.3.2. External Interrupts .................................................................................... 80 9.3.3. Interrupt Priorities ..................................................................................... 80 9.3.4. Interrupt Latency ...................................................................................... 80 9.3.5. Interrupt Register Descriptions................................................................. 81 9.4. Power Management Modes .............................................................................. 87 9.4.1. Idle Mode.................................................................................................. 87 9.4.2. Stop Mode ................................................................................................ 88 10 ...
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... Counter/Timer with Auto-Reload...................................... 173 18.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 174 18.2.Timer 2 .......................................................................................................... 179 18.2.1.16-bit Timer with Auto-Reload................................................................ 179 18.2.2.8-bit Timers with Auto-Reload................................................................ 180 18.3.Timer 3 .......................................................................................................... 183 18.3.1.16-bit Timer with Auto-Reload................................................................ 183 18.3.2.8-bit Timers with Auto-Reload................................................................ 184 19. Programmable Counter Array ............................................................................. 187 C8051F330/1, C8051F330D Rev. 1.2 5 ...
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... C8051F330/1, C8051F330D 19.1.PCA Counter/Timer ........................................................................................ 188 19.2.Capture/Compare Modules ............................................................................ 189 19.2.1.Edge-triggered Capture Mode................................................................ 190 19.2.2.Software Timer (Compare) Mode........................................................... 192 19.2.3.High-Speed Output Mode ...................................................................... 193 19.2.4.Frequency Output Mode ........................................................................ 194 19.2.5.8-Bit Pulse Width Modulator Mode......................................................... 195 19.2.6.16-Bit Pulse Width Modulator Mode....................................................... 196 19.3.Watchdog Timer Mode ................................................................................... 197 19 ...
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... Table 2.1. Absolute Maximum Ratings ................................................................... 25 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ...................................................... 26 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1, C8051F330D............................... 27 Figure 4.1. MLP-20 Pinout Diagram (Top View) ...................................................... 29 Table 4.2. MLP-20 Package Dimensions................................................................ 30 Figure 4.2. MLP-20 Package Drawing ..................................................................... 30 Figure 4 ...
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... Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data...... 48 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ........ 48 Table 5.1. ADC0 Electrical Characteristics ............................................................. 49 6. 10-Bit Current Mode DAC (IDA0, C8051F330 and C8051F330D only) Figure 6.1. IDA0 Functional Block Diagram ............................................................. 51 Figure 6.2. IDA0 Data Word Mapping ...................................................................... 52 Figure 6 ...
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... Figure 15.1. SMBus Block Diagram ....................................................................... 125 Figure 15.2. Typical SMBus Configuration ............................................................. 126 Figure 15.3. SMBus Transaction ............................................................................ 127 Table 15.1. SMBus Clock Source Selection........................................................... 130 Figure 15.4. Typical SMBus SCL Generation......................................................... 131 Table 15.2. Minimum SDA Setup and Hold Times ................................................. 131 C8051F330/1, C8051F330D Rev. 1.2 9 ...
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... C8051F330/1, C8051F330D Figure 15.5. SMB0CF: SMBus Clock/Configuration Register ................................ 132 Figure 15.6. SMB0CN: SMBus Control Register.................................................... 134 Table 15.3. Sources for Hardware Changes to SMB0CN ...................................... 135 Figure 15.7. SMB0DAT: SMBus Data Register...................................................... 136 Figure 15.8. Typical Master Transmitter Sequence................................................ 137 Figure 15.9. Typical Master Receiver Sequence.................................................... 138 Figure 15 ...
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... Figure 19.12. PCA0MD: PCA Mode Register......................................................... 201 Figure 19.13. PCA0CPMn: PCA Capture/Compare Mode Registers..................... 202 Figure 19.14. PCA0L: PCA Counter/Timer Low Byte............................................. 203 Figure 19.15. PCA0H: PCA Counter/Timer High Byte ........................................... 203 Figure 19.16. PCA0CPLn: PCA Capture Module Low Byte ................................... 203 C8051F330/1, C8051F330D Rev. 1.2 11 ...
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... C8051F330/1, C8051F330D Figure 19.17. PCA0CPHn: PCA Capture Module High Byte.................................. 203 20. C2 Interface Figure 20.1. C2ADD: C2 Address Register ............................................................ 205 Figure 20.2. DEVICEID: C2 Device ID Register..................................................... 205 Figure 20.3. REVID: C2 Revision ID Register ........................................................ 206 Figure 20.4. FPCTL: C2 Flash Programming Control Register .............................. 206 Figure 20.5. FPDAT: C2 Flash Programming Data Register.................................. 206 Figure 20 ...
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... Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and /RST pins are tolerant of input signals The C8051F330/1 are available in a 20- pin MLP package and the C8051F330D is available in a 20-pin DIP package. Block diagrams are included in Figure 1 ...
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... C8051F330/1, C8051F330D Table 1.1. Product Selection Guide C8051F330 25 8k 768 C8051F330D 25 8k 768 C8051F331 25 8k 768 Rev. 1.2 MLP-20 DIP-20 - MLP-20 ...
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... Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.1. C8051F330 and C8051F330D Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24 ...
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... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F330/1, C8051F330D family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compil- ers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard ...
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... Additional Features The C8051F330/1, C8051F330D SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... C8051F330/1, C8051F330D 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing ...
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... On-Chip Debug Circuitry The C8051F330/1, C8051F330D devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that pro- vides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, break- points, and single stepping ...
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... C8051F330/1, C8051F330D devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1, C8051F330D Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “ ...
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... Serial Ports The C8051F330/1, C8051F330D Family includes an SMBus/I enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully imple- mented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.6. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers ...
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... Analog to Digital Converter The C8051F330 and C8051F330D devices include an on-chip 10-bit SAR ADC with a 16-channel differen- tial input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both pos- itive and negative ADC inputs. Ports0-1 are available as an ADC inputs ...
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... Comparators C8051F330/1, C8051F330D devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asyn- chronous) output. Comparator response time is programmable, allowing the user to select between high- speed and low-power modes ...
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... Current Output DAC The C8051F330 and C8051F330D device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full- scale changes and supports jitter-free updates for waveform generation ...
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... This is a stress rating only and functional operation of the devices at those or any other condi- tions above those indicated in the operation listings of this specification is not implied. Exposure to maxi- mum rating conditions for extended periods may affect device reliability. C8051F330/1, C8051F330D Conditions Min Typ – ...
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... C8051F330/1, C8051F330D 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage V Digital Supply Current with DD = 2.7 V, Clock = 25 MHz CPU active 2.7 V, Clock = 1 MHz 2.7 V, Clock = 80 kHz 2.7 V, Clock = 32 kHz ...
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... Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1, C8051F330D Pin Pin Name ‘F330/1 ‘F330D GND 2 5 /RST C2CK P2. C2D P0. VREF P0 IDA0 P0. XTAL1 P0. XTAL2 P0 P0 C8051F330/1, C8051F330D Type Description Power Supply Voltage. Ground. D I/O Device Reset. Open-drain output of internal POR or monitor. An external source can initiate a system reset by driving this pin low for at least 10 µ ...
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... C8051F330/1, C8051F330D Table 4.1. Pin Definitions for the C8051F330/1, C8051F330D (Continued) Pin Pin Name ‘F330/1 ‘F330D P0. CNVSTR Type Description D I/O or Port 0.6. See Section ADC0 External Convert Start or IDA0 Update Source Input. See Section 5 and Section 6 D I/O or Port 0 ...
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... GND P0.0 1 GND 2 VDD 3 /RST/C2CK 4 P2.0/C2D 5 Figure 4.1. MLP-20 Pinout Diagram (Top View) C8051F330/1, C8051F330D C8051F330/1 Top View GND Rev. 1.2 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 29 ...
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... C8051F330/1, C8051F330D Bottom View DETAIL Side View DETAIL Figure 4.2. MLP-20 Package Drawing Rev. 1.2 Table 4.2. MLP-20 Package Dimensions MM MIN TYP MAX A 0.80 0.90 1. 0.02 0. 0.65 1.00 A3 — 0.25 — b 0.18 0.23 0.30 D — 4.00 — D2 2.00 2.15 2.25 E — ...
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... L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.3. Typical MLP-20 Solder Paste Mask C8051F330/1, C8051F330D Top View 0.60 mm 0.60 mm 0.30 mm 0. Rev. 1.2 0. ...
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... C8051F330/1, C8051F330D 0.50 mm 0.20 mm Optional GND Connection 0. 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.4. Typical MLP-20 Landing Diagram 32 Top View E2 E Rev. 1.2 0.85 mm ...
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... C8051F330/1, C8051F330D Figure 4.5. DIP-20 Pinout Diagram (Top View) Rev. 1 ...
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... C8051F330/1, C8051F330D 20 Top View PIN 1 IDENTIFIER 1 Side View Pin Dimensions (Bottom View) b1 Base c c1 Metal b Figure 4.6. DIP-20 Package Drawing 34 Table 4.3. DIP-20 Package Dimensions Side View E 0.015" Rev. 1.2 INCHES MIN TYP MAX - - 0.210 0.015 - - 0.115 0.130 0.195 0.014 0.018 ...
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... ADC (ADC0, C8051F330 and C8051F330D only) The ADC0 subsystem for the C8051F330 and C8051F330D consists of two analog multiplexers (referred to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation- register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data con- version modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
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... C8051F330/1, C8051F330D 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: Ports0-1, the on-chip temperature sensor, or the positive power supply ( following may be selected as the negative input: Ports0-1, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...
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... The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 -50 Figure 5.2. Typical Temperature Sensor Transfer Function C8051F330/1, C8051F330D V = 2.86(TEMP TEMP 0 50 Rev. 1 the TEMP ) + 776 mV C ...
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... C8051F330/1, C8051F330D 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN ...
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... SAR Clocks Low Power AD0TM=1 or Convert SAR Clocks Track or AD0TM=0 Convert Figure 5.3. 10-Bit ADC Track and Conversion Example Timing C8051F330/1, C8051F330D Section “5.3.3. Settling Time Requirements” on page Track Convert Track or Convert Convert B. ADC0 Timing for Internal Trigger Source ...
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... C8051F330/1, C8051F330D 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu- racy required for the conversion ...
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... Figure 5.5. AMX0P: AMUX0 Positive Channel Select Register C8051F330/1, C8051F330D R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P0.0 P0.1 P0.2 P0 ...
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... C8051F330/1, C8051F330D Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. ...
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... For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read ‘0’. Figure 5.9. ADC0L: ADC0 Data Word LSB Register C8051F330/1, C8051F330D R/W R/W R/W ...
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... C8051F330/1, C8051F330D R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit6: AD0TM: ADC0 Track Mode Bit. ...
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... Figure 5.11. ADC0GTH: ADC0 Greater-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Greater-Than Data Word Figure 5.12. ADC0GTL: ADC0 Greater-Than Data Low Byte Register C8051F330/1, C8051F330D R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 ...
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... C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word Figure 5.13. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC0 Less-Than Data Word Figure 5.14. ADC0LTL: ADC0 Less-Than Data Low Byte Register ...
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... ADC0LTH:ADC0LTL 0x1FC0 0x1040 VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL 0x0FC0 AD0WINT not affected 0x0000 0 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data C8051F330/1, C8051F330D ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF 0x0081 VREF x (128/1024) 0x0080 0x007F AD0WINT=1 0x0041 VREF x (64/1024) ...
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... C8051F330/1, C8051F330D 5.4.2. Window Detector In Differential Mode Figure 5.17 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF x (511/512). Output codes are represented as 10-bit 2’ ...
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... Linearity Absolute Accuracy Gain Gain Error* Offset Offset Error* Power Supply Current supplied to ADC0) Power Supply Rejection *Note: Represents one standard deviation from the mean. C8051F330/1, C8051F330D Conditions Min DC Accuracy — Guaranteed Monotonic — — — — the 5th harmonic — ...
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... C8051F330/1, C8051F330D 50 Rev. 1.2 ...
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... Current Mode DAC (IDA0, C8051F330 and C8051F330D only) The C8051F330 and C8051F330D device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see Figure 6.3). When IDA0EN is set to ‘ ...
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... C8051F330/1, C8051F330D 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘ ...
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... Figure 6.3. IDA0CN: IDA0 Control Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: IDA0 Data Word High-Order Bits. Bits 7-0 are the most-significant bits of the 10-bit IDA0 Data Word. Figure 6.4. IDA0H: IDA0 Data Word MSB Register C8051F330/1, C8051F330D R R Bit4 Bit3 Bit2 ...
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... C8051F330/1, C8051F330D R/W R Bit7 Bit6 Bit5 Bits 7-6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5-0: UNUSED. Read = 000000b, Write = don’t care. Figure 6.5. IDA0L: IDA0 Data Word LSB Register Table 6.1. IDAC Electrical Characteristics -40 to +85 ° ...
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... Voltage Reference (C8051F330 and C8051F330D only) The Voltage reference MUX on C8051F330/1, C8051F330D devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source or the internal reference, REFSL should be set to ‘0’. To use source, REFSL should be set to ‘ ...
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... C8051F330/1, C8051F330D Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference used as voltage reference. Bit2: TEMPE: Temperature Sensor Enable Bit. ...
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... Input Current Sample Rate = 200 ksps; VREF = ADC Bias Generator BIASE = ‘1’ or AD0EN = ‘1’ or Reference Bias Generator REFBE = ‘1’ or TEMPE = ‘1’ or C8051F330/1, C8051F330D Conditions Internal Reference (REFBE = 1) 25 °C ambient bypass 0.1 µF ceramic bypass no bypass cap External Reference (REFBE = 0) 3 ...
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... C8051F330/1, C8051F330D 58 Rev. 1.2 ...
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... Comparator0 C8051F330/1, C8051F330D devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asyn- chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when in when the system clock is not active ...
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... C8051F330/1, C8051F330D The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA ...
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... Positive Hysteresis = 20 mV. Bits1-0: CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Figure 8.3. CPT0CN: Comparator0 Control Register C8051F330/1, C8051F330D R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
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... C8051F330/1, C8051F330D R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 Bit7 Bit6 Bit5 Bits7-4: CMX0N2-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N3 CMX0N2 CMX0N1 CMX0N0 Bits3-0: CMX0P2-CMX0P0: Comparator0 Positive Input MUX Select. ...
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... UNUSED. Read = 00b, Write = don’t care. Bits1-0: CP0MD1-CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode CP0MD1 CP0MD0 Figure 8.5. CPT0MD: Comparator0 Mode Selection Register C8051F330/1, C8051F330D R CP0FIE - - CP0MD1 CP0MD0 00000010 Bit4 Bit3 Bit2 CP0 Response Time (TYP) 0 100 ns 1 ...
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... C8051F330/1, C8051F330D Table 8.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 0, Vcm = 1.5 V Response Time: * Mode 1, Vcm = 1.5 V Response Time: * Mode 2, Vcm = 1.5 V Response Time: * Mode 3, Vcm = 1.5 V Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 ...
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... ACCUMULATOR RESET CLOCK STOP IDLE C8051F330/1, C8051F330D Section 18), an enhanced full-duplex UART (see description Section 17), 256 bytes of internal RAM, 128 byte (Section 9.2.6), and 17 Port I/O (see description in ...
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... C8051F330/1, C8051F330D With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. Clocks to Execute 1 Number of Instructions 26 Programming and Debugging Support In-system programming of the Flash program memory and communication with on-chip debug support logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2) ...
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... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F330/1, C8051F330D does not support off-chip data or program memory). In the CIP-51, the MOVX instruction can be used to access on-chip XRAM or on-chip program memory space implemented as re-programmable Flash memory ...
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... C8051F330/1, C8051F330D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct ...
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... RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ rel Jump if A equals zero C8051F330/1, C8051F330D Description Boolean Manipulation Program Branching Rev. 1.2 Clock Bytes Cycles ...
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... C8051F330/1, C8051F330D Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal Compare immediate to Register and jump if not ...
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... Byte Sectors) 0x0000 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F330/1, C8051F330D implements 8k bytes of this program memory space as in-system, re-programmable Flash memory, organized in a contig- uous block from addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved. ...
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... C8051F330/1, C8051F330D 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 73
... ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ADC0H 0xBE ADC0 High ADC0L 0xBD ADC0 Low C8051F330/1, C8051F330D PCA0CPL0 PCA0CPH0 OSCLCN IT01CF P0SKIP P1SKIP TMR2L TMR2H ADC0GTL ADC0GTH ADC0LTL AMX0P ADC0CF ADC0L OSCICL SPI0DAT ...
Page 74
... C8051F330/1, C8051F330D Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ADC0LTH 0xC6 ADC0 Less-Than Compare Word High ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low AMX0N 0xBA AMUX0 Negative Channel Select ...
Page 75
... TMR3RLH 0x93 Timer/Counter 3 Reload High TMR3RLL 0x92 Timer/Counter 3 Reload Low V DD Monitor Control VDM0CN 0xFF XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 C8051F330/1, C8051F330D Rev. 1.2 Page 202 202 203 203 201 151 150 132 134 ...
Page 76
... C8051F330/1, C8051F330D 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys- tem function ...
Page 77
... This is a bit-addressable, general purpose flag for use under software control. Bit0: PARITY: Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Figure 9.6. PSW: Program Status Word C8051F330/1, C8051F330D R/W R/W R/W R/W RS1 ...
Page 78
... C8051F330/1, C8051F330D R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. ...
Page 79
... Table 9.4 on page 81. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051F330/1, C8051F330D Rev. 1.2 79 ...
Page 80
... C8051F330/1, C8051F330D 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON or edge sensitive ...
Page 81
... SMB0 0x003B RESERVED 0x0043 ADC0 Window Compare 0x004B ADC0 Conversion 0x0053 Complete Programmable Counter 0x005B Array Comparator0 0x0063 RESERVED 0x006B Timer 3 Overflow 0x0073 C8051F330/1, C8051F330D Priority Pending Flag Order Top None N/A N/A 0 IE0 (TCON. TF0 (TCON. IE1 (TCON. TF1 (TCON.7) Y RI0 (SCON0 ...
Page 82
... C8051F330/1, C8051F330D 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...
Page 83
... Timer 0 interrupt set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Figure 9.10. IP: Interrupt Priority C8051F330/1, C8051F330D R/W R/W R/W R/W PS0 PT1 ...
Page 84
... C8051F330/1, C8051F330D R/W R/W R/W ET3 Reserved ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. Bit6: RESERVED. Read = 0. Must Write 0. Bit5: ECP0: Enable Comparator0 (CP0) Interrupt ...
Page 85
... Bit0: PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Figure 9.12. EIP1: Extended Interrupt Priority 1 C8051F330/1, C8051F330D R/W R/W R/W PPCA0 PADC0 PWADC0 Reserved ...
Page 86
... C8051F330/1, C8051F330D R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 18.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits6-4: IN1SL2-0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde- pendent of the Crossbar ...
Page 87
... Idle mode indefi- nitely, waiting for an external stimulus to wake up the system. Refer to Timer Reset” on page 92 for more information on the use and configuration of the WDT. C8051F330/1, C8051F330D // set IDLE bit // ... followed by a 3-cycle dummy instruction ; set IDLE bit ...
Page 88
... C8051F330/1, C8051F330D 9.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher- als are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop Mode ...
Page 89
... Px.x C0RSEF Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler C8051F330/1, C8051F330D for information on selecting and configuring details the use of the Watchdog Timer). VDD Power On Reset Supply Monitor + '0' - Enable PCA (Software Reset) WDT SWRSF EN Operation System Reset Figure 10 ...
Page 90
... C8051F330/1, C8051F330D 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the RST V increases ( DD ramp time is defined as how fast V power-on and DD monitor reset timing ...
Page 91
... V Bit6: DD STAT: DD Status. This bit indicates the current power supply status ( below the above the Bits5-0: Reserved. Read = 000000b. Write = don’t care. Figure 10.3. VDM0CN: C8051F330/1, C8051F330D Monitor drop below monitor is enabled and a software reset monitor Bit4 Bit3 Bit2 V DD Monitor cannot generate system V DD Monitor output) ...
Page 92
... C8051F330/1, C8051F330D 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST pin specifications ...
Page 93
... Read: Last reset was a power- indeterminate. Write: Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not /RST pin. 1: Source of last reset was /RST pin. Figure 10.4. RSTSRC: Reset Source Register C8051F330/1, C8051F330D R/W R R/W SWRSF WDTRSF MCDRSF Bit4 Bit3 Bit2 V DD monitor reset ...
Page 94
... C8051F330/1, C8051F330D Table 10.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL /RST Output Low Voltage V /RST Input High Voltage /RST Input Low Voltage /RST Input Pullup Current /RST = 0 POR Threshold (V ) RST Missing Clock Detector Time- Time from last system clock ...
Page 95
... Step 4. Write the first key code to FLKEY: 0xA5. Step 5. Write the second key code to FLKEY: 0xF1. Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE and PSEE bits. C8051F330/1, C8051F330D Section “20. C2 Interface” Rev. 1 Monitor ...
Page 96
... Steps 5-7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 11.1. Flash Electrical Characteristics VDD = 2.7 to 3.6 V; -40 to +85 ºC unless otherwise specified. Parameter Flash Size C8051F330/1, C8051F330D Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 512 bytes at addresses 0x1E00 to 0x1FFF are reserved ...
Page 97
... Access limit set according to the FLASH security lock byte Figure 11.2. Flash Program Memory Map C8051F330/1, C8051F330D 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) 0x0000 to 0x03FF (first two Flash pages) and 0x1C00 to 0x1DFF (Lock Byte Page) C8051F330/1 ...
Page 98
... C8051F330/1, C8051F330D The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Accessing Flash from the C2 debug interface: 1 ...
Page 99
... When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. Figure 11.4. FLKEY: Flash Lock and Key Register C8051F330/1, C8051F330D R/W - ...
Page 100
... C8051F330/1, C8051F330D R/W R/W R/W FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bit7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen- cies below 10 MHz, disabling the Flash one-shot will increase system power consumption ...
Page 101
... External RAM The C8051F330/1, C8051F330D devices include 512 bytes of RAM mapped into the external data mem- ory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in Figure 12 ...
Page 102
... C8051F330/1, C8051F330D 102 Rev. 1.2 ...
Page 103
... The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 13.2. On C8051F330/1, C8051F330D devices, OSCICL is factory calibrated to obtain a 24.5 MHz base fre- quency. Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 112. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 104
... This register determines the internal oscillator period. When set to 0000000b, the H-F oscil- lator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. On C8051F330/1, C8051F330D devices, the reset value is factory cali- brated to generate an internal oscillator frequency of 24.5 MHz. ...
Page 105
... Programmable Internal Low-Frequency (L-F) Oscillator All C8051F330/1, C8051F330D devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see Figure 13.4). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’ ...
Page 106
... C8051F330/1, C8051F330D 13.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13. MΩ ...
Page 107
... C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where f = frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts Figure 13.5. OSCXCN: External Oscillator Control Register C8051F330/1, C8051F330D R/W R R/W R/W - XFCN2 XFCN1 Bit4 Bit3 ...
Page 108
... C8051F330/1, C8051F330D 13.3.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 13.5 (OSCXCN register). For example ...
Page 109
... Capacitor values depend on crystal specifications Figure 13.6. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram C8051F330/1, C8051F330D XTAL1 XTAL2 22pF* Rev. 1.2 109 ...
Page 110
... C8051F330/1, C8051F330D 13.3.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation ...
Page 111
... SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 01: SYSCLK derived from the External Oscillator circuit. 10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD bits in register OSCLCN. 11: reserved. Figure 13.7. CLKSEL: Clock Select Register C8051F330/1, C8051F330D R ...
Page 112
... C8051F330/1, C8051F330D Table 13.1. Internal Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified DD A Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b 25 °C, Oscillator Supply Current V (from DD ) OSCICN Power Supply Sensitivity Constant Temperature Temperature Sensitivity ...
Page 113
... SPI 2 SMBus 2 CP0 Outputs SYSCLK 4 PCA 2 Lowest T0, T1 Priority 8 P0 (P0.0-P0. (P1.0-P1.7) Figure 14.1. Port I/O Functional Block Diagram C8051F330/1, C8051F330D XBR0, XBR1, PnMDOUT, PnSKIP Registers PnMDIN Registers Priority Decoder P0 8 I/O Cells P1 Digital 8 I/O Crossbar Cells Rev. 1.2 P0.0 P0.7 P1 ...
Page 114
... C8051F330/1, C8051F330D /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram 114 VDD VDD (WEAK) GND Rev. 1.2 PORT PAD ...
Page 115
... P0SKIP[7:0] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. Figure 14.3. Crossbar Priority Decoder with No Pins Skipped C8051F330/1, C8051F330D P0 CNVSTR ...
Page 116
... C8051F330/1, C8051F330D SF Signals VREF IDA x1 x2 PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[7:0] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins ...
Page 117
... Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F330/1, C8051F330D Rev. 1.2 117 ...
Page 118
... C8051F330/1, C8051F330D CP0AE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. Bit4: CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. ...
Page 119
... PCA0ME: PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. Figure 14.6. XBR1: Port I/O Crossbar Register 1 C8051F330/1, C8051F330D R/W R/W R R/W T0E ECIE ...
Page 120
... C8051F330/1, C8051F330D 14.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports2-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...
Page 121
... Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. Figure 14.11. P1: Port1 Register C8051F330/1, C8051F330D R/W R/W R/W R/W Bit4 ...
Page 122
... C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. ...
Page 123
... Figure 14.15. P2: Port2 Register Bit7 Bit6 Bit5 Bits7-1: Unused. Read = 0000000b. Write = don’t care. Bit0: Output Configuration Bit for P2.0. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. Figure 14.16. P2MDOUT: Port2 Output Mode Register C8051F330/1, C8051F330D Bit4 Bit3 Bit2 Bit1 (bit addressable ...
Page 124
... C8051F330/1, C8051F330D Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output High Voltage –10 mA, Port I/O push-pull 8 µA Output Low Voltage Input High Voltage Input Low Voltage ...
Page 125
... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation Figure 15.1. SMBus Block Diagram C8051F330/1, C8051F330D Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL Control Data Path SDA Control Control SMB0DAT FILTER Rev. 1 serial bus ...
Page 126
... C8051F330/1, C8051F330D 15.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
Page 127
... LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win- ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. C8051F330/1, C8051F330D SLA5-0 R/W D7 ...
Page 128
... C8051F330/1, C8051F330D 15.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. ...
Page 129
... Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in tion Register” on page 130. C8051F330/1, C8051F330D for more details on transmission 133; Table 15.4 provides a quick SMB0CN decoding refer- Section “15.4.1. SMBus Configura- Rev. 1.2 Section ...
Page 130
... C8051F330/1, C8051F330D 15.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 131
... SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 15.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F330/1, C8051F330D T SCL High Timeout High ...
Page 132
... C8051F330/1, C8051F330D R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. Bit6: INH: SMBus Slave Inhibit. ...
Page 133
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 15.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 15.4 for SMBus sta- tus decoding using the SMB0CN register. C8051F330/1, C8051F330D Rev. 1.2 133 ...
Page 134
... C8051F330/1, C8051F330D R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. ...
Page 135
... ACK/NACK received. SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F330/1, C8051F330D Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. ...
Page 136
... C8051F330/1, C8051F330D 15.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 137
... Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 15.8. Typical Master Transmitter Sequence C8051F330/1, C8051F330D W A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP ...
Page 138
... C8051F330/1, C8051F330D 15.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
Page 139
... Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 15.10. Typical Slave Receiver Sequence C8051F330/1, C8051F330D A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK ...
Page 140
... C8051F330/1, C8051F330D 15.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...
Page 141
... NACK received. A master data or address byte was transmitted; ACK received. 1100 C8051F330/1, C8051F330D Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. ...
Page 142
... C8051F330/1, C8051F330D Table 15.4. SMBus Status Decoding Values Read Current SMbus State A master data byte was received; 1000 slave byte was transmitted slave byte was transmitted; 0100 Slave byte was transmitted STOP was detected while an 0101 addressed Slave Transmitter. 142 Typical Response Options Acknowledge received byte ...
Page 143
... X A slave byte was received; ACK 0000 Lost arbitration while transmitting data byte as master. C8051F330/1, C8051F330D Typical Response Options Acknowledge received ACK requested. Do not acknowledge received address. Acknowledge received requested. Do not acknowledge received address. Reschedule failed transfer; do not acknowledge received Abort failed transfer. ...
Page 144
... C8051F330/1, C8051F330D 144 Rev. 1.2 ...
Page 145
... UART0 interrupt (transmit complete or receive complete). Write to SBUF Stop Bit Start Tx Clock UART Baud Rate Generator Rx Clock Start Figure 16.1. UART0 Block Diagram C8051F330/1, C8051F330D 146). Received data buffering allows SFR Bus TB8 SBUF SET (TX Shift CLR Zero Detector ...
Page 146
... C8051F330/1, C8051F330D 16.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 16.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 147
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 BIT SPACE BIT TIMES BIT SAMPLING Figure 16.4. 8-Bit UART Timing Diagram C8051F330/1, C8051F330D TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR OR TX ...
Page 148
... C8051F330/1, C8051F330D 16.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
Page 149
... Master Slave Device Device Figure 16.6. UART Multi-Processor Mode Interconnect Diagram C8051F330/1, C8051F330D Slave Slave Device Device Rev. 1.2 V+ ...
Page 150
... C8051F330/1, C8051F330D R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’t care. ...
Page 151
... SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. Figure 16.8. SBUF0: Serial (UART0) Port Data Buffer Register C8051F330/1, C8051F330D R/W R/W R/W ...
Page 152
... C8051F330/1, C8051F330D Table 16.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15% Notes: 1. SCA1-SCA0 and T1M bit definitions can be found Don’ ...
Page 153
... Notes: 1. SCA1-SCA0 and T1M bit definitions can be found Don’t care. C8051F330/1, C8051F330D Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1-SCA0 tor Divide Source (pre-scale Factor select) 96 SYSCLK XX 192 SYSCLK ...
Page 154
... C8051F330/1, C8051F330D Table 16.4. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 ...
Page 155
... Notes: 1. SCA1-SCA0 and T1M bit definitions can be found Don’t care. C8051F330/1, C8051F330D Frequency: 11.0592 MHz Oscilla- Timer Clock SCA1-SCA0 tor Divide Source (pre-scale Factor select) 48 SYSCLK XX 96 SYSCLK ...
Page 156
... C8051F330/1, C8051F330D Table 16.6. Timer Settings for Standard Baud Rates Using an External Oscillator Target Baud Baud Rate Rate% (bps) Error 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 ...
Page 157
... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus C8051F330/1, C8051F330D SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT ...
Page 158
... C8051F330/1, C8051F330D 17.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 159
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 17.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F330/1, C8051F330D Rev. 1.2 159 ...
Page 160
... C8051F330/1, C8051F330D Master Device 1 Figure 17.2. Multiple-Master Mode Connection Diagram Master Device Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Device GPIO Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 160 NSS ...
Page 161
... The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. C8051F330/1, C8051F330D Rev. 1.2 161 ...
Page 162
... C8051F330/1, C8051F330D 17.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock ...
Page 163
... NSS (4-Wire Mode) Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) C8051F330/1, C8051F330D Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 6 ...
Page 164
... C8051F330/1, C8051F330D 17.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures ...
Page 165
... SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. Figure 17.9. SPI0CN: SPI0 Control Register C8051F330/1, C8051F330D R/W R/W R/W TXBMT Bit4 Bit3 Bit2 Bit1 161) ...
Page 166
... C8051F330/1, C8051F330D R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register ...
Page 167
... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.12. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.13. SPI Master Timing (CKPHA = 1) C8051F330/1, C8051F330D T MCKL T T MIS MIH T MCKL T MIH Rev ...
Page 168
... C8051F330/1, C8051F330D NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.14. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
Page 169
... MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH Last SCK Edge to MISO Change T SLH (CKPHA = 1 ONLY) *Note equal to one period of the device system clock (SYSCLK). SYSCLK C8051F330/1, C8051F330D Min SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK — ...
Page 170
... C8051F330/1, C8051F330D 170 Rev. 1.2 ...
Page 171
... As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. C8051F330/1, C8051F330D Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload 61) ...
Page 172
... C8051F330/1, C8051F330D The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “14.1. Priority Crossbar Decoder” on page 115 pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock ...
Page 173
... TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register INT01CF (see page 59 for details on the external input signals /INT0 and /INT1). Pre-scaled Clock SYSCLK T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 18.2. T0 Mode 2 Block Diagram C8051F330/1, C8051F330D Section “8.3.2. External Interrupts” on CKCON TMOD INT01CF ...
Page 174
... C8051F330/1, C8051F330D 18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 175
... This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see Figure 8.13). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. Figure 18.4. TCON: Timer Control Register C8051F330/1, C8051F330D R/W R/W R/W R/W ...
Page 176
... C8051F330/1, C8051F330D R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter INT01CF (see Figure 8.13). ...
Page 177
... System clock divided System clock divided External clock divided by 8 Note: External clock divided synchronized with the system clock. Figure 18.6. CKCON: Clock Control Register C8051F330/1, C8051F330D R/W R/W R/W T2ML T1M T0M SCA1 Bit4 Bit3 Bit2 Prescaled Clock Rev. 1.2 ...
Page 178
... C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 18.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL1: Timer 1 Low Byte. ...
Page 179
... CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 18.11. Timer 2 16-Bit Mode Block Diagram C8051F330/1, C8051F330D To SMBus TL2 Overflow TCLK TR2 TL2 TH2 TMR2RLL TMR2RLH Reload Rev. 1.2 To ADC, SMBus TF2H Interrupt TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK 179 ...
Page 180
... C8051F330/1, C8051F330D 18.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.12. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. ...
Page 181
... Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. Figure 18.13. TMR2CN: Timer 2 Control Register C8051F330/1, C8051F330D R/W R/W R/W ...
Page 182
... C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. Figure 18.14. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLH: Timer 2 Reload Register High Byte. ...
Page 183
... TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TL3) overflow from 0xFF to 0x00. CKCON T3XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 18.18. Timer 3 16-Bit Mode Block Diagram C8051F330/1, C8051F330D TCLK TR3 TL3 TH3 TMR3RLL TMR3RLH Reload Rev. 1.2 To ADC TF3H Interrupt TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK 183 ...
Page 184
... C8051F330/1, C8051F330D 18.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers operate in auto-reload mode as shown in Figure 18.12. TMR3RLL holds the reload value for TL3; TMR3RLH holds the reload value for TH3. The TR3 bit in TMR3CN handles the run control for TH3. TL3 is always running when configured for 8-bit Mode ...
Page 185
... Timer 3 external clock selection is the system clock divided by 12. 1: Timer 3 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. Figure 18.20. TMR3CN: Timer 3 Control Register C8051F330/1, C8051F330D R/W R/W R/W ...
Page 186
... C8051F330/1, C8051F330D R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. Figure 18.21. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLH: Timer 3 Reload Register High Byte. ...
Page 187
... Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 19.3 for details. Capture/Compare C8051F330/1, C8051F330D SYSCLK/12 SYSCLK/4 Timer 0 Overflow PCA 16-Bit Counter/Timer ...
Page 188
... C8051F330/1, C8051F330D 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. ...
Page 189
... K n PCA Counter/ Timer Overflow ECCF0 PCA Module 0 (CCF0) ECCF1 PCA Module 1 (CCF1) ECCF2 PCA Module 2 (CCF2) Figure 19.3. PCA Interrupt Block Diagram C8051F330/1, C8051F330D MAT TOG PWM ECCF Capture triggered by positive edge CEXn Capture triggered by negative edge on CEXn Capture triggered by transition on ...
Page 190
... C8051F330/1, C8051F330D 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
Page 191
... ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn Figure 19.5. PCA Software Timer Mode Diagram C8051F330/1, C8051F330D PCA0CPLn PCA0CPHn Enable 16-bit Comparator PCA PCA0L PCA0H Timebase Rev. 1.2 PCA Interrupt PCA0CN Match 1 191 ...
Page 192
... C8051F330/1, C8051F330D 19.2.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode ...
Page 193
... Reset PCA0CPMn Write PCA0CPHn ENB Figure 19.7. PCA Frequency Output Mode C8051F330/1, C8051F330D F PCA ---------------------------------------- - F = CEXn × 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev. 1.2 PCA0CPHn TOGn 0 CEXn Crossbar Port I/O 1 193 ...
Page 194
... C8051F330/1, C8051F330D 19.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. ...
Page 195
... Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn PCA Timebase Figure 19.9. PCA 16-Bit PWM Mode C8051F330/1, C8051F330D ( 65536 PCA0CPn – ---------------------------------------------------- - = 65536 PCA0CPHn PCA0CPLn match Enable 16-bit Comparator S R PCA0H PCA0L Overflow Rev. 1.2 ) CEXn SET Q Crossbar Port I/O Q CLR 195 ...
Page 196
... C8051F330/1, C8051F330D 19.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. ...
Page 197
... The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.6, this results in a WDT timeout interval of 256 system clock cycles. Table 19.3 lists some example timeout intervals for typical sys- tem clocks. C8051F330/1, C8051F330D ( × ) ...
Page 198
... C8051F330/1, C8051F330D Table 19.3. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 3,060,000 3,060,000 3,060,000 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. 2. Internal oscillator reset frequency. ...
Page 199
... This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Figure 19.11. PCA0CN: PCA Control Register C8051F330/1, C8051F330D R R R/W ...
Page 200
... C8051F330/1, C8051F330D R/W R/W R/W CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. ...