C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet - Page 10

• Manufacturer Part Number: C8051F330
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F330

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F330/1, C8051F330D
16. UART0
17. Enhanced Serial Peripheral Interface (SPI0)
10
Figure 15.5. SMB0CF: SMBus Clock/Configuration Register ................................ 132
Figure 15.6. SMB0CN: SMBus Control Register.................................................... 134
Table 15.3. Sources for Hardware Changes to SMB0CN ...................................... 135
Figure 15.7. SMB0DAT: SMBus Data Register...................................................... 136
Figure 15.8. Typical Master Transmitter Sequence................................................ 137
Figure 15.9. Typical Master Receiver Sequence.................................................... 138
Figure 15.10. Typical Slave Receiver Sequence.................................................... 139
Figure 15.11. Typical Slave Transmitter Sequence................................................ 140
Table 15.4. SMBus Status Decoding...................................................................... 141
Figure 16.1. UART0 Block Diagram ....................................................................... 145
Figure 16.2. UART0 Baud Rate Logic .................................................................... 146
Figure 16.3. UART Interconnect Diagram .............................................................. 147
Figure 16.4. 8-Bit UART Timing Diagram............................................................... 147
Figure 16.5. 9-Bit UART Timing Diagram............................................................... 148
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................... 149
Figure 16.7. SCON0: Serial Port 0 Control Register .............................................. 150
Figure 16.8. SBUF0: Serial (UART0) Port Data Buffer Register ............................ 151
Table 16.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ....
Table 16.2. Timer Settings for Standard Baud Rates Using an External Oscillator 152
Table 16.3. Timer Settings for Standard Baud Rates Using an External Oscillator 153
Table 16.4. Timer Settings for Standard Baud Rates Using an External Oscillator 154
Table 16.5. Timer Settings for Standard Baud Rates Using an External Oscillator 155
Table 16.6. Timer Settings for Standard Baud Rates Using an External Oscillator 156
Figure 17.1. SPI Block Diagram ............................................................................. 157
Figure 17.2. Multiple-Master Mode Connection Diagram ....................................... 160
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Figure 17.5. Master Mode Data/Clock Timing ........................................................ 162
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 163
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 163
Figure 17.8. SPI0CFG: SPI0 Configuration Register ............................................. 164
Figure 17.9. SPI0CN: SPI0 Control Register.......................................................... 165
Figure 17.10. SPI0CKR: SPI0 Clock Rate Register ............................................... 166
Figure 17.11. SPI0DAT: SPI0 Data Register.......................................................... 166
Figure 17.12. SPI Master Timing (CKPHA = 0)...................................................... 167
Figure 17.13. SPI Master Timing (CKPHA = 1)...................................................... 167
Figure 17.14. SPI Slave Timing (CKPHA = 0)........................................................ 168
Figure 17.15. SPI Slave Timing (CKPHA = 1)........................................................ 168
Table 17.1. SPI Slave Timing Parameters ............................................................. 169
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160
160
Rev. 1.2