HD6412350F20 Renesas Electronics America, HD6412350F20 Datasheet - Page 228

• Manufacturer Part Number: HD6412350F20
• Description: IC H8S MPU ROMLESS 5V 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD6412350F20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 Instruction Descriptions
2.2.59 (3)
SHLL (SHift Logical Left)
Operation
Rd (left logical shift)
Assembly-Language Format
SHLL.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 15) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 212 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHLL (W)
Mnemonic
SHLL.W
C
Rd
MSB
b15
Operands
Rd
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 15.
2nd byte
1
Instruction Format
cleared to 0.
cleared to 0.
—
I
rd
UI H
—
—
3rd byte
LSB
b0
—
U
N
0
4th byte
Z
Shift Logical
V
0
States
No. of
C
1