HD6413007F20 Renesas Electronics America, HD6413007F20 Datasheet - Page 464
HD6413007F20
Manufacturer Part Number
HD6413007F20
Description
IC H8 MCU ROMLESS 5V 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13007F20V.pdf
(798 pages)
Specifications of HD6413007F20
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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13. Serial Communication Interface
Bit 5⎯Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode,
the parity bit is neither added nor checked, regardless of the PE bit setting.
Bit 5
PE
0
1
Note:
Bit 4⎯Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is only valid when the
PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit
setting is ignored in synchronous mode, or when parity addition and checking is disabled in
asynchronous mode.
Bit 4
O/E
0
1
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
Bit 3⎯Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mod no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
0
1
Notes: 1. One stop bit (with value 1) is added to the end of each transmitted character.
Rev.5.00 Sep. 12, 2007 Page 434 of 764
REJ09B0396-0500
* When PE bit is set to 1, an even or odd parity bit is added to transmit data according to
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
2. Two stop bits (with value 1) are added to the end of each transmitted character.
the even or odd parity mode selection by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Description
Parity bit not added or checked
Parity bit added and checked*
Description
Even parity*
Odd parity*
Description
1 stop bit*
2 stop bits*
1
2
2
1
(Initial value)
(Initial value)
(Initial value)
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