SAF-XC164CS-16F40F BB Infineon Technologies, SAF-XC164CS-16F40F BB Datasheet - Page 23

• Manufacturer Part Number: SAF-XC164CS-16F40F BB
• Description: IC MCU 16BIT FLASH TQFP-100-16
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-16F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 79
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 8.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 128.0 KByte
• For Use With: B158-H8962-X-X-7600IN - KIT EASY XC164CSMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: FX164CS16F40FBBNP; FX164CS16F40FBBXT; SAFXC164CS16F40FBBT; SP000094312; SP000224552

3.3
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
Based on these hardware provisions, most of the XC164CS’s instructions can be
executed in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For
Data Sheet
CPU
M AC
P refetch
M u ltip ly
B ranch
FIFO
ID X 0
ID X 1
M A H
Q X 0
Q X 1
U nit
U nit
U nit
+ /-
+ /-
Central Processing Unit (CPU)
CPU Block Diagram
C S P
C P U C O N 1
C P U C O N 2
R etu rn
M R W
M C W
M S W
M A L
S tack
Q R 0
Q R 1
+ /-
IP
IFU
D ivisio n U n it
M u ltip ly U n it
ZE R O S
D P P 0
D P P 1
D P P 2
D P P 3
P S W
M D C
M D H
Exception
Injection/
V E C S E G
Handler
B it-M a sk-G e n .
TF R
B a rre l-S h ifte r
21
S P S E G
S T K O V
S T K U N
O N E S
M D L
S P
+ /-
ADU
ALU
RF
DM U
PM U
G P R s
2-S tage
R 15
R 14
5-S tage
G P R s
R 1
R 0
B uffer
R 15
R 14
P refetch
R 1
R 0
P ipeline
C P
G P R s
P ipeline
R 15
R 14
R 1
R 0
IPIP
W B
Functional Description
Peripherals
Flash/RO M
m ca04917_x.vsd
DPRAM
DSRAM
PSRAM
Derivatives
V2.3, 2006-08
EBC
G P R s
R 1 5
R 1 4
XC164CS
R 1
R 0