MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 23

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

As DV
old set by the VDBR bits, the RESET pin is pulled low,
µC and peripheral activity stops, and most, but not all
of the register bits are set to their default state. This
includes the VDBR bits, which retain their value if DV
falls below the BOR threshold, but not below the POR
threshold.
Once DV
scenarios:
• If DV
• If DV
• If DV
Refer to the MAXQ7665/MAXQ7666 User’s Guide for
detailed programming information, and a more thor-
ough description of POR and brownout behavior.
The MAXQ7665A–MAXQ7665D core logic supply,
DV
on-chip 3.3V, 50mA linear regulator. To use the on-chip
linear regulator, ensure the DV
a load of approximately 50mA and connect digital input
REGEN to GNDIO. If using an external supply, connect
the regulated 3.3V supply to DV
input REGEN to DV
used, bring up DV
The MAXQ7665A–MAXQ7665D oscillator module is the
master clock generator that supplies the system clock
for the µC core and all of the peripheral modules. The
high-frequency (HF) oscillator is designed to operate
with an 8MHz crystal. Alternatively, the on-chip RC
oscillator can be used in applications that do not
require precise timing. Due to its RISC design, the
RESET pin remains low, and the µC remains in the
reset state.
threshold, then begins rising above the BOR thresh-
old, the RESET pin is released, and the µC jumps to
the reset vector (8000h in the utility ROM). This is
similar to the DV
previous scenario, except there is no power-up
counter delay and some of the register bits are set
to BOR values rather than POR values. See Tables 3
and 5 for the reset behavior of specific bits. In par-
ticular, the retained VDBR setting, if higher than the
default value of 00b, allows a potentially more robust
brownout recovery closer to or above the minimum
flash operating level of +3.0V.
bits are reset, and any DV
is identical to the power-up case described above.
See Tables 3 and 5 for reset behavior of specific bits.
DD
, can be supplied by a 3.3V external supply or the
DD
DD
DD
DD
DD
continues to fall below the DV
falls below the 1.2V POR threshold, all register
has entered BOR, there are a few possible
remains below the BOR threshold, the
stops falling before reaching the POR
Internal 3.3V Linear Regulator
DDIO
______________________________________________________________________________________
DD
DDIO
power-up case described in the
before DV
System Clock Generator
. If the linear regulator is not
DD
DDIO
recovery from that point
DD
16-Bit RISC Microcontroller-Based
DD
and connect digital
supply can support
.
Smart Data-Acquisition Systems
DD
BOR thresh-
DD
MAXQ7665A–MAXQ7665D execute most instructions in
a single SYSCLK period. The oscillator module contains
all of the primary clock-generation circuitry. Figure 6
shows a block diagram of the system clock module.
The MAXQ7665A–MAXQ7665D contain many features
for generating a master clock signal timing source:
• Internal, fast-starting, 7.6MHz RC oscillator elimi-
• Internal high-frequency oscillator that can drive an
• External high-frequency clock input (8MHz)
• Selectable internal capacitors for HF crystal oscillator
• Power-up timer
• Power-saving management modes
• Fail-safe modes
The watchdog timer serves as a time-base generator,
an event timer, or a system supervisor. The primary
function of the watchdog timer is to supervise software
execution, watching for stalled or stuck software. The
watchdog timer performs a controlled system restart
when the µP fails to write to the watchdog timer register
before a selectable timeout interval expires. In some
designs, the watchdog timer is also used to implement
a real-time operating system (RTOS) in the µC. When
used to implement an RTOS, a watchdog timer typically
has four objectives:
1) To detect if a system is operating normally
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or
4) To detect if some lower priority tasks are not getting
Figure 6. High-Frequency and RC Oscillator Block Diagram
XOUT
XIN
nates external crystal
external 8MHz crystal
more tasks
to run because of higher priority tasks
RCE
XT
XTAL
HFE
OSC
OSC
RC
HF
EXTHF
MUX
HFRCCLK
Watchdog Timer
CLOCK
DIVIDE
CD0
SYSCLK
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