MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 27

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

each incoming message, before accepting an incom-
ing message. This feature allows the CAN unit to
directly support the use of higher CAN protocols, which
make use of the first and/or second byte of data as a
part of the acceptance layer for storing incoming mes-
sages. Each message center can also be programmed
independently to perform testing of the incoming data
with or without the use of the global masks.
Global controls and status registers in the CAN unit
allow the µC to evaluate error messages, validate new
data and the location of such data, establish the bus
timing for the CAN bus, establish the identification
mask bits, and verify the source of individual mes-
sages. In addition, each message center is individually
equipped with the necessary status and controls to
establish directions, interrupt generation, identification
mode (standard or extended), data field size, data sta-
tus, automatic remote frame request and acknowledg-
Figure 11a. UART Synchronous Mode (Mode 0)
SCON0.1
FLAG =
______________________________________________________________________________________
TI
DIVIDE
BY 12
0
SYSCLK
SCON0.0
FLAG =
RI
DIVIDE
1
RDSBUF
LDSBUF
BY 4
16-Bit RISC Microcontroller-Based
SERIAL
INTERRUPT
BAUD
CLOCK
BUFFER
SERIAL
LOAD
Smart Data-Acquisition Systems
OUTPUT SHIFT REGISTER
SERIAL I/O
CONTROL
CLOCK
DATA
SBUF0
RECEIVE
BUFFER
SERIAL
SHIFT
READ
SI
ment, and masked or nonmasked identification accep-
tance testing.
Serial interfacing is provided through one (UTX/URX)
8051-style universal synchronous/asynchronous receiv-
er/transmitter (UART) capable of interfacing with a LIN
transceiver. Figure 11a shows the UART block diagram
in synchronous mode and Figure 11b shows asynchro-
nous mode. The UART allows the device to conveniently
communicate with other RS-232 interface-enabled
devices, as well as PCs and serial modems when paired
with an external RS-232 line driver/receiver. The UART
can detect framing errors and indicate the condition
through a user-accessible software bit. The time base of
the serial port is derived from either a division of the sys-
tem clock or the dedicated baud clock generator. The
UART is capable of supporting LIN protocol implementa-
tion in software when using one of the timers for autobaud
CLOCK
S0
RD
RECEIVE SHIFT REGISTER
LATCH
RECEIVE DATA BUFFER
DATA BUS
OUTPUT
UTX
INPUT
SBUF0
URX
WR
UART Interface
27