MCP6041T-I/OT Microchip Technology, MCP6041T-I/OT Datasheet - Page 12

• Manufacturer Part Number: MCP6041T-I/OT
• Description: IC OPAMP 1UA 1.4V SNGLR-R SOT235
• Manufacturer: Microchip Technology

Specifications of MCP6041T-I/OT

• Slew Rate: 0.003 V/µs
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 14kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 0.6µA
• Current - Output / Channel: 20mA
• Voltage - Supply, Single/dual (±): 1.4 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Channels: 1
• Common Mode Rejection Ratio (min): 60 dB
• Input Offset Voltage: 3 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 6 V
• Supply Voltage (min): 1.4 V
• Technology: CMOS
• Voltage Gain Db: 115 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MCP6041T-I/OT; MCP6041T-I/OTTR

MCP6041/2/3/4
4.0
The MCP6041/2/3/4 family of op amps is manufactured
using Microchip’s state of the art CMOS process These
op amps are unity gain stable and suitable for a wide
range of general purpose, low power applications.
See Microchip’s related MCP6141/2/3/4 family of op
amps for applications, at a gain of 10 V/V or higher,
needing greater bandwidth.
4.1
4.1.1
The MCP6041/2/3/4 op amps are designed to not
exhibit phase inversion when the input pins exceed the
supply voltages.
exceeding both supplies with no phase inversion.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
and V
resistors R
of the input pins. Diodes D
pins (V
DS21669C-page 12
SS
. They also clamp any voltages that go too far
V
V
V
IN
IN
DD
IN
SS
Characteristics”).
+
–) from going too far below ground, and the
DD
+ and V
APPLICATIONS INFORMATION
Rail-to-Rail Input
B
). The input ESD diodes clamp the inputs
1
Figure
; their breakdown voltage is high enough to
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
and R
IN
Figure 2-10
4-1. This structure was chosen to
2
–) from going too far above V
limit the possible current drawn out
Simplified Analog Input ESD
Stage
Input
1
and D
Figure 4-2
shows an input voltage
2
prevent the input
Bond
Pad
shows
V
IN
DD
–
, and
the
IN
+
dump any currents onto V
shown, resistors R
through D
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
the diodes D
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
V
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
Figure
need to limit the useable voltage range.
4.1.3
The input stage of the MCP6041/2/3/4 op amps uses
two differential input stages in parallel. One operates at
a low common mode input voltage (V
other operates at a high V
device operates with a V
and 300 mV below V
measured at V
ensure proper operation.
There are two transitions in input behavior as V
changed. The first occurs, when V
V
V
best distortion performance with non-inverting gains,
avoid these regions of operation.
IN
SS
DD
V
V
–) should be very small.
1
2
+ 0.4V, and the second occurs when V
– 0.5V (see
2-33. Applications that are high impedance may
R
R
1
1
1
2
R
R
and D
and R
NORMAL OPERATION
1
>
>
1
2
D
and D
1
V
V
SS
SS
CM
D
2
2
Figure 2-3
2
CM
.
. In this case, the currents through
– (minimum expected V
– (minimum expected V
= V
1
2
) is below ground (V
need to be limited by some other
SS
and R
Protecting the Analog
SS
© 2008 Microchip Technology Inc.
. The input offset voltage is
MCP604X
CM
– 0.3V and V
DD
2 mA
2 mA
CM
V
up to 300 mV above V
and
2
R
. When implemented as
. With this topology, the
DD
3
also limit the current
Figure
CM
2-6). For the
DD
CM
), while the
1
2
CM
)
)
+ 0.3V to
SS
V
is near
IN
OUT
is near
); see
+ and
CM
DD
is