MCP617-I/SN Microchip Technology, MCP617-I/SN Datasheet - Page 15

• Manufacturer Part Number: MCP617-I/SN
• Description: IC OPAMP 2.3V DUAL R-R 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP617-I/SN

• Slew Rate: 0.08 V/µs
• Operating Temperature: -40°C ~ 85°C
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 190kHz
• Current - Input Bias: 15nA
• Voltage - Input Offset: 150µV
• Current - Supply: 19µA
• Current - Output / Channel: 17mA
• Voltage - Supply, Single/dual (±): 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: General Purpose
• No. Of Amplifiers: 2
• Bandwidth: 190kHz
• Supply Voltage Range: 2.3V To 5.5V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Number Of Channels: 2
• Voltage Gain Db: 120 dB
• Common Mode Rejection Ratio (min): 80 dB
• Input Offset Voltage: 0.15 mV
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details

4.0
The MCP616/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process,
which includes PNP transistors. These op amps are
unity-gain stable and suitable for a wide range of
general purpose applications.
4.1
4.1.1
The MCP616/7/8/9 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages.
ing the supply voltage without any phase reversal.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the V
“Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”).
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
the resistors R
out of the input pins. Diodes D
input pins (V
V
implemented as shown, resistors R
the current through D
© 2008 Microchip Technology Inc.
SS
DD
IN
. They also clamp any voltages that go too far
+ and V
, and dump any currents onto V
V
V
V
IN
DD
SS
+
DD
APPLICATIONS INFORMATION
Rail-to-Rail Inputs
B
Figure 2-36
). The input ESD diodes clamp the inputs
Figure
; their breakdown voltage is high enough to
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
IN
IN
–) from going too far below ground, and
1
+ and V
and R
4-1. This structure was chosen to
1
shows the input voltage exceed-
2
Simplified Analog Input ESD
and D
limit the possible current drawn
IN
Stage
Input
–) from going too far above
2
.
IN
1
+ and V
and D
1
and R
Bond
Pad
2
IN
prevent the
– pins (see
DD
2
Figure 4-2
V
also limit
. When
IN
–
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of
resistors R
diodes D
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
V
A significant amount of current can flow out of the
inputs when the common mode voltage (V
ground (V
high impedance may need to limit the usable voltage
range.
4.1.3
The inputs of the MCP616/7/8/9 op amps connect to a
differential PNP input stage. The common mode input
voltage range (V
systems (V
that the amplifier input behaves linearly as long as the
common mode input voltage (V
specified V
4.2
The MCP616/7/8/9 family of op amps have a PNP input
differential pair that gives good DC performance. They
have very low input offset voltage (±150 µV, maximum)
at T
(sourced out of the inputs).
There must be a DC path to ground (or power supply)
from both inputs, or the op amp will not bias properly.
The DC resistances seen by the op amp inputs (R
and R
than 100 kΩ, to minimize the total DC offset.
IN
V
V
–) should be very small.
1
2
A
= +25°C, with a typical bias current of -15 nA
4
||R
1
DC Offsets
R
R
SS
5
R
R
1
2
1
and D
CMR
SS
NORMAL OPERATION
in
D
1
2
). (See
>
>
and R
), but does not include V
1
V
V
Figure
limits (V
SS
SS
CMR
2
D
MCP616/7/8/9
2
needs to be limited by some other
– (minimum expected V
– (minimum expected V
2
. In this case, current through the
Figure
) includes ground in single-supply
4-3) need to be equal and less
Protecting the Analog
SS
to V
2-36.) Applications that are
MCP61X
2 mA
2 mA
V
R
DD
DD
CM
3
–0.9V at +25°C).
) is kept within the
DS21613C-page 15
DD
. This means
CM
1
2
)
)
) is below
IN
+ and
1
||R
2