BD7542F-E2 Rohm Semiconductor, BD7542F-E2 Datasheet - Page 13

• Manufacturer Part Number: BD7542F-E2
• Description: OP AMP I/O FULL SWING HV 8-SOP
• Manufacturer: Rohm Semiconductor

Specifications of BD7542F-E2

• Slew Rate: 0.6 V/µs
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 600kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 400µA
• Current - Output / Channel: 1mA
• Voltage - Supply, Single/dual (±): 5 V ~ 14.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOP
• Op Amp Type: CMOS
• No. Of Amplifiers: 2
• Bandwidth: 0.6MHz
• Supply Voltage Range: ± 2.5V To ± 7.25V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 45 dB
• Input Offset Voltage: 9 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 9 V, 12 V
• Supply Current: 0.65 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Dual Supply Voltage: +/- 3 V, +/- 5 V
• Maximum Dual Supply Voltage: +/- 7.25 V
• Minimum Dual Supply Voltage: +/- 2.5 V
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 14.5 V
• Supply Voltage (min): 5 V
• Technology: CMOS
• Voltage Gain Db: 95 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: BD7542F-E2TR

BD7561G,BD7561SG,BD7541G,BD7541SG,
BD7562F/FVM,BD7562SF/FVM, BD7542F/FVM,BD7542SF/FVM
●Schematic diagram
●Test circuit1 NULL method
© 2009 ROHM Co., Ltd. All rights reserved.
www.rohm.com
Input Offset Voltage
Large Signal Voltage Gain
Common-mode Rejection Ratio
(Input Common-mode Voltage Range)
Power Supply Rejection Ratio
-Calculation-
1. Input Offset Voltage (Vio)
2. Large Signal Voltage Gain (Av)
3. Common-mode Rejection Ratio (CMRR)
4. Power Supply Rejection Ratio (PSRR)
VDD,VSS,EK,Vicm Unit : [V]
Vicm
Parameter
RS ＝ 50[Ω]
RS ＝ 50[Ω]
50[kΩ]
0.015[μF]
Ri=1[MΩ]
Ri=1[MΩ]
SW2
SW1
0.015[μF]
Fig. 93. Schematic diagram
Fig. 94. Test circuit 1 (one channel only)
VF1
VF2
VF3
VF4
VF5
VF6
VF7
VF
VDD
VSS
DUT
CMRR
Vio
PSRR
Av
=
=
20Log
ON
ON
ON
ON
S1
VRL
SW3
=
1+Rf/Rs
=
RL
|VF1|
20Log
20Log
Vo
13/20
2×(1+Rf/Rs)
Rf=50[kΩ]
ON
ON
ON
ON
S2
|VF2-VF3|
0.1[μF]
1.8×(1+Rf/Rs)
3.8×(1+Rf/Rs)
EK
[V]
|VF6-VF7|
|VF4-VF5|
1000[pF]
500[kΩ]
OFF
OFF
OFF
500[kΩ]
ON
S3
[dB]
VDD
14.5
12
12
12
5
[dB]
[dB]
NULL
-15[V]
15[V]
VSS
0
0
0
0.01[μF]
0
-11.5
-0.5
-2.5
EK
-6
-6
VF
Vicm
Technical Note
2009.05 - Rev.A
12
12
6
0
0
Calculation
1
2
3
4