AD8041ARZ Analog Devices Inc, AD8041ARZ Datasheet - Page 14

• Manufacturer Part Number: AD8041ARZ
• Description: IC OPAMP VF R-R LP LDIST 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8041ARZ

• Slew Rate: 170 V/µs
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• -3db Bandwidth: 170MHz
• Current - Input Bias: 1.2µA
• Voltage - Input Offset: 2000µV
• Current - Supply: 5.8mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Voltage Feedback
• No. Of Amplifiers: 1
• Bandwidth: 170MHz
• Supply Voltage Range: 3V To 12V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8041
To test this, the differential gain and differential phase were
measured for the AD8041 while the supplies were varied. As the
lower supply is raised to approach the video signal, the first effect
to be observed is that the sync tips become compressed before
the differential gain and differential phase are adversely affected.
Thus, there must be adequate swing in the negative direction to
pass the sync tips without compression.
As the upper supply is lowered to approach the video, the differ-
ential gain and differential phase were not significantly adversely
affected until the difference between the peak video output and
the supply reached 0.6 V. Thus, the highest video level should
be kept at least 0.6 V below the positive supply rail.
Taking the above into account, it was found that the optimal
point to bias the noninverting input is at 2.2 V dc. Operating at
this point, the worst-case differential gain is measured at 0.06%
and the worst-case differential phase is 0.06°.
The ac coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower fre-
quency band edge of 30 Hz. The resistances at the various ac
coupling points—especially at the output—are quite small. In
order to minimize phase shifts and baseline tilt, the large value
capacitors are required. For video system performance that is
not to be of the highest quality, the value of these capacitors can
be reduced by a factor of up to five with only a slightly observ-
able change in the picture quality.
Sync Stripper
Some RGB monitor systems use only three cables total and
carry the synchronizing signals along with the green (G) signal
on the same cable. The sync signals are pulses that go in the
negative direction from the blanking level of the G signal.
In some applications like prior to digitizing component video
signals with A/D converters, it is desirable to remove or strip the
sync portion from the G signal. Figure 14 is a schematic of a
circuit using the AD8041 running on a single 5 V supply that
performs this function.
GROUND
V
BLANK
V
IN
+0.4
GREEN W/SYNC
75
Figure 14. Single-Supply Sync Stripper
1k
(2X V
R1
0.8V
BLANK
3
2
AD8041
1k
R2
)
5V
4
7
0.1 F
6
GROUND
10 F
75
(MONITOR)
GREEN W/OUT SYNC
75
–14–
Referring to Figure 15, the green plus sync signal is output
from an ADV7120, a single-supply triple video DAC. Because
the DAC is single supply, the lowest level of the sync tip is at
ground or slightly above. The AD8041 is set for a gain of two to
compensate for the divide by two of the output terminations.
The reference voltage for R1 should be twice the dc blanking
level of the G signal. If the blanking level is at ground and the
sync tip is negative as in some dual-supply systems, then R1 can
be tied to ground. In either case, the output will have the sync
removed and have the blanking level at ground.
Layout Considerations
The specified high speed performance of the AD8041 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing.
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large (0.47 µF
to 10 µF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Figure 15. Single-Supply Sync Stripper
100
0%
90
10
500mV
500mV
10 s
REV. B