MCP6S92-E/SN Microchip Technology, MCP6S92-E/SN Datasheet
MCP6S92-E/SN
Specifications of MCP6S92-E/SN
Available stocks
Related parts for MCP6S92-E/SN
MCP6S92-E/SN Summary of contents
Page 1
... These specifications support single- supply applications needing flexible performance or multiple inputs. The one-channel MCP6S91 and the two-channel MCP6S92 are available in 8-pin PDIP, SOIC and MSOP packages. The two-channel MCP6S93 is available in a 10-pin MSOP package. All parts are fully specified from -40°C to +125°C. ...
Page 2
... A — ±0.0004 — %/° and the inverting input of the internal amplifier. The MCP6S92 has REF OUT is coupled to the internal amplifier and the PSRR spec describes PSRR+ only pin be tied directly to ground to avoid noise problems. SS are not tested in production; they are set by design and characterization. ...
Page 3
... V and the inverting input of the internal amplifier. The MCP6S92 has REF OUT is coupled to the internal amplifier and the PSRR spec describes PSRR+ only pin be tied directly to ground to avoid noise problems. SS are not tested in production; they are set by design and characterization. ...
Page 4
... See Table 4-1 for a list of typical numbers and Figure 2-25 for the frequency response versus gain and e include ladder resistance noise. See Figure 2-12 for 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V / pF, SI and SCK are tied low and CS is tied high. ...
Page 5
... Not tested in production. Set by design and characterization. 2: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay time (t DO fall times of 5 ns. Maximum f SCK 2004 Microchip Technology Inc. = 25° +2.5V to +5.5V / pF, SI and SCK are tied low and CS is tied high. ...
Page 6
... Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 10L-MSOP Note 1: Operation in this range must not cause T 2004 Microchip Technology Inc. MCP6S91/2/3 = +2.5V to +5.5V GND Sym Min Typ Max ...
Page 7
... PGA Shutdown Timing Diagram (must enter correct commands before CS goes high CSSC SCK (first 16 bits out are always zeros) FIGURE 1-4: Detailed SPI™ Serial Interface Timing; SPI 0,0 Mode. 2004 Microchip Technology Inc OUT FIGURE 1-3: Diagram. t OFF Hi 1/f SCK t ...
Page 8
... – O_LIN REF SS 2004 Microchip Technology Inc 1/f SCK t DO The end points of this line are – 0.3V. Figure 1-6 shows the relationship between DD the gain and offset specifications referred to in the electrical specifications as follows: EQUATION 1- The DC Gain Drift ( G/ T ...
Page 9
... G G FIGURE 1-7: Output Voltage INL with the standard condition REF SS 2004 Microchip Technology Inc. 1.1.4 DIFFERENT V Some of the plots in Section 2.0 “Typical Performance Curves”, have the conditions The equations and figures above are easily REF DD modified for these conditions. The ideal V ...
Page 10
... DC Gain Error (%) FIGURE 2-2: DC Gain Error, G 16% 597 Samples 14 -40 to +125°C A 12% 10 Ladder Resistance Drift (%/°C) FIGURE 2-3: Ladder Resistance Drift. 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF 35% 600 Samples 30 25% T 20% 15% 10 FIGURE 2-4: 26% 600 Samples ...
Page 11
... Input Offset Voltage Mismatch (µV) FIGURE 2-8: Input Offset Voltage Mismatch. 1000 100 100 1000 0 100 1k Frequency (Hz) FIGURE 2-9: Input Noise Voltage Density vs. Frequency. 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF 24% 22% 20% 18% 16% 14% 12% 10 FIGURE 2-10: 3.0 = 10.0 µ ...
Page 12
... FIGURE 2-18: Shutdown Mode. MCP6S91/2/3 = GND V/V, SS REF 2.5V DD Input Referred V = 5.5V DD 100 1000 10000 100000 1000000 100 1k 10k 100k 1M Frequency (Hz) PSRR vs. Frequency. MCP6S92 5. +125° +85°C A Input Voltage (V) Input Bias Current vs. Input = 5. Quiescent Current in Shutdown (pA) Quiescent Current in DS21908A-page 12 ...
Page 13
... Power Supply Voltage (V) FIGURE 2-20: DC Output Non-Linearity vs. Supply Voltage. 1000 V = 5.5V DD 100 10 1 0.1 1 Output Plus Ladder Current Magnitude (mA) FIGURE 2-21: Output Voltage Headroom vs. Output Plus Ladder Current (circuit in Figure 4-2). 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF ...
Page 14
... Bandwidth vs. Capacitive Load. 1 Measurement kHz V = 2.0V OUT P 5. 0.001 1.5V L 0.0001 1.E+02 1.E+03 1.E+04 100 1k 10k Frequency (Hz) FIGURE 2-27: THD plus Noise vs. Frequency OUT P-P 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF 1.E+08 10 100M FIGURE 2-28: Load + 1000 ...
Page 15
... V is "ON" OUT 0.5 0.0 0.E+00 1.E+00 2.E+00 3.E+00 4.E+00 5.E+00 6.E+00 7.E+00 8.E+00 9.E+00 Time (1 µs/div) FIGURE 2-33: Output Voltage vs. Shutdown Mode. 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF 300 5.0 = 5.0V 250 4.5 200 4.0 150 3.5 100 3 ...
Page 16
... V – – 2.5V: V – – -50 - Ambient Temperature (°C) FIGURE 2-38: Output Voltage Headroom vs. Ambient Temperature. 2004 Microchip Technology Inc. = +25° +2.5V to +5.5V and pF 1 V/V 1.1 V 1.0 0.9 0.8 0.7 0.6 0 +125° 0.2 T 0.1 0.0 2.0 2.5 ...
Page 17
... The internal MUX selects which one is amplified to the output. 3.3 External Reference Voltage (V The V pin, which is an analog input, should REF voltage between V and V (the MCP6S92 has tied internally The voltage at this pin REF SS shifts the output voltage. ...
Page 18
... PGA Block Diagram. 4.1 Input MUX The MCP6S91 has one input, while the MCP6S92 and MCP6S93 have two inputs (see Figure 4-1). For the lowest input current, float unused inputs. Tying these pins to a voltage near the active channel’s bias voltage also works well ...
Page 19
... Current beyond ±2 mA can cause possible reliability problems. Applications that exceed this rating must be externally limited with an input resistor, as shown in Figure 4-3. 2004 Microchip Technology Inc (Maximum expected V R ...
Page 20
... The resistive ladder is always connected between V and V ; even in shutdown. This means that the REF OUT output resistance will be on the order with a path for output signals to appear at the input. 2004 Microchip Technology Inc. pin must be – 0.3V and SS is REF ). Staying within MCP6S91/2/3 ...
Page 21
... FIGURE 5-2: Serial Bus Sequence for the PGA; SPI™ 1,1 Mode (see Figure 1-5). 2004 Microchip Technology Inc. Chain Configuration”, covers applications using multiple 16-bit words. SO goes low after CS goes high; it has a push-pull output that does not go into a high-Z state ...
Page 22
... Shutdown does not toggle. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. After power-up, and when the power supply voltage dips below the minimum valid V nal register data and state machine may need to be reset. This is accomplished as described before. Use ...
Page 23
... Gain of +2 010 = Gain of +4 011 = Gain of +5 100 = Gain of +8 101 = Gain of +10 110 = Gain of +16 111 = Gain of +32 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. U-x U-x U-x W-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 24
... CHANGING THE CHANNEL If the Instruction register is programmed to address the Channel register, the multiplexed inputs of the MCP6S92 and MCP6S93 can be changed using Register 5-3. REGISTER 5-3: CHANNEL REGISTER U-x U-x — — bit 7 bit 7-1 Unimplemented: Read as ‘0’ (reserved for future use) ...
Page 25
... The MCP6S91 and MCP6S92 can only be used at the far end of the daisy- chain, because they do not have a serial data out (SO) pin. As shown in Figure 5-4 and Figure 5-5, both SI and SO data are sent in 16-bit (2 byte) words ...
Page 26
... SCK SI Instruction Byte for Device 2 SO (first 16 bits out are always zeros) FIGURE 5-5: Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 1,1 Mode. 2004 Microchip Technology Inc. MCP6S91/2 10111213141516 Data Byte Instruction Byte for Device 1 for Device 2 Instruction Byte ...
Page 27
... Figure 6-2) improves the internal amplifier’s ISO stability by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. 2004 Microchip Technology Inc pin at REF FIGURE 6-2: Capacitive Loads. ...
Page 28
... This capacitor needs to be large enough to overcome gain (or crosstalk) peak- ing, yet small enough to allow a reasonable signal bandwidth. 2004 Microchip Technology Inc. 6.3.4 SIGNAL COUPLING The input pins of the MCP6S91/2/3 family of PGAs are high-impedance. This makes them especially suscepti- ble to capacitively-coupled noise ...
Page 29
... FIGURE 6-8: V OUT Range. 6.4.4 MULTIPLE SENSOR AMPLIFIER The multiple-channel PGAs (MCP6S92 and MCP6S93) allow the user to select which sensor appears on the output (see Figure 6-9). These devices can also change the gain to optimize performance for each sensor. Sensor # 0 Sensor # 1 FIGURE 6-9: Inputs ...
Page 30
... EXPANDED INPUT PGA Figure 6-10 shows cascaded MCP6S28 MCP6S92s PGAs that provide input channels. Obviously, Sensors #1-8 have a high total gain range available, as explained in Section 6.4.3 “Extended Gain Range PGA”. These devices can be daisy- chained (Section 5.3 “Daisy-Chain Configuration”). ...
Page 31
... PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead PDIP (300 mil) (MCP6S91, MCP6S92) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) (MCP6S91, MCP6S92) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP (MCP6S91, MCP6S92) XXXXX YWWNNN 10-Lead MSOP (MCP6S93) XXXXX YWWNNN Legend: XX...X Customer specific information* ...
Page 32
... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2004 Microchip Technology Inc ...
Page 33
... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2004 Microchip Technology Inc Units ...
Page 34
... Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 2004 Microchip Technology Inc Units INCHES ...
Page 35
... Lead Width Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-021 2004 Microchip Technology Inc φ ...
Page 36
... NOTES: 2004 Microchip Technology Inc. MCP6S91/2/3 DS21908A-page 36 ...
Page 37
... One-channel PGA, PDIP package. b) MCP6S91-E/SN: One-channel PGA, SOIC package. c) MCP6S91-E/MS: One-channel PGA, MSOP package. a) MCP6S92-E/MS: Two-channel PGA, MSOP-8 package. b) MCP6S92T-E/MS: Tape and Reel, Two-channel PGA, MSOP-8 package. a) MCP6S93-E/UN: Two-channel PGA, MSOP-10 package. b) MCP6S93T-E/UN: Tape and Reel, Two-channel PGA, MSOP-10 package. DS21908A-page 37 ...
Page 38
... MCP6S91/2/3 NOTES: DS21908A-page 38 2004 Microchip Technology Inc. ...
Page 39
... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 40
... Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 2004 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4420-9895 Fax: 45-4420-9910 France - Massy Tel: 33-1-69-53-63-20 ...