MCP6S92-E/SN Microchip Technology, MCP6S92-E/SN Datasheet - Page 28

• Manufacturer Part Number: MCP6S92-E/SN
• Description: IC PGA 2CH R-R I/O SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6S92-E/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Amplifier Type: Programmable Gain
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 22 V/µs
• -3db Bandwidth: 18MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 400µV
• Current - Supply: 1mA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 1
• Available Set Gain: 30.1 dB (Typ)
• Input Offset Voltage: 4 mV @ 5.5 V
• Input Bias Current (max): 0.000001 uA (Typ) @ 5.5 V
• Operating Supply Voltage: 3 V or 5 V
• Supply Current: 1.6 mA @ 5.5V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP6SX2DM-PCTLPD - BOARD DAUGHTER PICTAIL MCP6SX2
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.2
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the V
ground plane. A multi-layer ceramic chip capacitor, or
high-frequency equivalent, works best.
Use a bulk bypass capacitor (2.2 µF to 10 µF) within
100 mm of the V
ground plane. A multi-layer ceramic chip capacitor,
tantalum or high-frequency equivalent, works best.
This capacitor may be shared with other nearby analog
parts.
6.3.3
The sources driving the inputs of the PGAs need to
have reasonably low source impedance at higher
frequencies. Figure 6-4 shows how the external source
impedance (R
and PGA package pin-to-pin capacitance (C
positive feedback voltage divider network. Feedback to
the selected channel may cause frequency response
peaking and step response overshoot and ringing.
Feedback to an unselected channel will produce
crosstalk.
FIGURE 6-4:
Figure 2-6 shows the crosstalk (referred to input) that
results when a hostile signal is connected to CH1, input
CH0 is selected and R
GND. A gain of +32 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing R
increases the crosstalk as expected. At a source
impedance of 10 k
response; this is due to positive feedback.
Most designs should use a source resistance (R
larger than 10 k . Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 k
must be used, place a capacitor in parallel to C
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk) peak-
ing, yet small enough to allow a reasonable signal
bandwidth.
 2004 Microchip Technology Inc.
V
IN
SUPPLY BYPASS
INPUT SOURCE IMPEDANCE
R
S
DD
S
C
), PGA package pin capacitance (C
P1
DD
pin. It must connect directly to the
there is noticeable peaking in the
pin. It needs to connect to the
Positive Feedback Path.
S
MCP6S9X
is connected from CH0 to
C
P2
P2
V
) form a
OUT
S
P1
) no
P1
to
S
)
6.3.4
The input pins of the MCP6S91/2/3 family of PGAs are
high-impedance. This makes them especially suscepti-
ble to capacitively-coupled noise. Using a ground plane
helps reduce this problem.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
6.3.5
Because the MCP6S91/2/3 PGAs’ frequency response
reaches unity gain at 64 MHz when G = 16 and 32, it is
important to use good PCB layout techniques. Any
parasitic-coupling at high-frequency might cause
undesired peaking. Filtering high-frequency signals
(i.e., fast edge rates) can help. To minimize high-
frequency problems:
• Use complete ground and power planes
• Use HF, surface-mount components
• Provide clean supply voltages and bypassing
• Keep traces short and straight
• Try a linear power supply (e.g., a LDO)
SIGNAL COUPLING
HIGH-FREQUENCY ISSUES
MCP6S91/2/3
DS21908A-page 28