AD8555ACP-REEL7 Analog Devices Inc, AD8555ACP-REEL7 Datasheet
AD8555ACP-REEL7
Specifications of AD8555ACP-REEL7
Related parts for AD8555ACP-REEL7
AD8555ACP-REEL7 Summary of contents
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FEATURES Very low offset voltage: 10 μV maximum over temperature Very low input offset voltage drift: 60 nV/°C maximum High CMRR minimum Digitally programmable gain and output offset voltage Single-wire serial interface Open and short wire fault detection ...
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AD8555 TABLE OF CONTENTS Electrical Specifications ................................................................... 3 Absolute Maximum Ratings ............................................................ 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 17 Gain Values .................................................................................. 18 Open Wire Fault Detection ....................................................... 19 ...
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ELECTRICAL SPECIFICATIONS Table 1. Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range ...
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AD8555 Parameter DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 DIGOUT Logic 1 Symbol Conditions 25°C w0 ...
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Table 2. Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection ...
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AD8555 Parameter DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time between Pulses at DIGIN Symbol Conditions 25° 25° ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 6 V Input Voltage VSS − 0 VDD + 0 Differential Input Voltage ±5.0 V Output Short-Circuit Indefinite Duration to VSS or VDD Storage Temperature Range −65°C ...
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AD8555 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 8 AD8555 FILT/DIGOUT 2 7 TOP VIEW DIGIN 3 6 (Not to Scale) VNEG 4 5 Figure 2. 8-Lead SOIC (Not Drawn to Scale) Table 5. Pin Configuration SOIC Pin No. Mnemonic ...
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TYPICAL PERFORMANCE CHARACTERISTICS –9 –6 – (μV) OS Figure 4. Input Offset Voltage Distribution 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 0 0.5 1.0 1.5 2.0 2.5 V (V) ...
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AD8555 100 10 1 –75 – TEMPERATURE (°C) Figure 10. Input Bias Current at VPOS, VNEG vs. Temperature 100 (V) CM Figure 11. Input Bias Current at VPOS, VNEG vs. Common-Mode ...
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SUPPLY VOLTAGE (V) Figure 16. Supply Current (I ) vs. Supply Voltage SY 3.0 2.5 2.0 1.5 1.0 0.5 –75 –50 – TEMPERATURE (°C) Figure 17. Supply ...
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AD8555 250 FREQUENCY (kHz) Figure 22. Input Voltage Noise Density vs. Frequency ( 500 kHz) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 TIME (1s/DIV) Figure 23. Low Frequency Input Voltage ...
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V = ±2. 1nF L OUTPUT BUFFER 100 S 0 0.1 1.0 10.0 LOAD CAPACITANCE (nF) Figure 28. Output Buffer Positive Overshoot ...
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AD8555 6 SUPPLY VOLTAGE OUT 0 TIME (100 μ s/DIV) Figure 34. Power-On Response at −40°C 150 145 140 135 130 125 120 115 110 105 100 –75 –50 – TEMPERATURE ...
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T 2 TIME (10μs/DIV) Figure 40. Large Signal Response ±2. 100 FREQUENCY (kHz) Figure 41. Output Impedance vs. Frequency OUT Figure 42. ...
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AD8555 + 0.1μ AD8555 8 0.1μF –V 10kΩ 1kΩ 10kΩ OUT Figure 46. Settling Time 0. 0.1 μ AD8555 8 0.1 μ F –V ...
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THEORY OF OPERATION A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the differential amplifier. A1 and A2 are auto-zeroed op amps that minimize input offset errors. P1 and P2 are digital potentiome- ters, guaranteed ...
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AD8555 GAIN VALUES Table 6. First Stage Gain vs. Gain Code First Stage First Stage Gain Code First Stage Gain Gain Code 0 4.000 32 1 4.015 33 2 4.030 34 3 4.045 35 4 4.060 36 5 4.075 37 ...
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OPEN WIRE FAULT DETECTION The inputs to A1 and A2, VNEG and VPOS, each have a com- parator to detect whether VNEG or VPOS exceeds a threshold voltage, nominally VDD − 1 (VNEG > VDD − 1.1 V) ...
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AD8555 WAVEFORM CODE 0 1 Table 10. Timing Specifications Timing Parameter Description t Pulse Width for Loading 0 into Shift Register w0 t Pulse Width for Loading 1 into Shift Register w1 t Width ...
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Initial State Initially, all the polysilicon fuses are intact. Each parameter has the value 0 assigned (see Table 12). Table 12. Initial State before Programming Second Stage Gain Code = 0 Second Stage Gain = 17.5 First Stage Gain Code ...
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AD8555 VA0 IN01 VA1 IN02 VA2 IN03 VB0 IN04 VB1 IN05 VB2 IN06 VB3 IN07 VB4 IN08 VB5 IN09 EOR18 VB6 IN10 VC0 IN11 VC1 IN12 VC2 IN13 VC3 IN14 VC4 IN15 VC5 IN16 VC6 IN17 VC7 IN18 Table 13. ...
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After the second stage gain, first stage gain, and output offset have been programmed, DAT_SUM should be computed and the parity bit should be set equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should not be blown in ...
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AD8555 Suggested Programming Procedure 1. Set VDD and VSS to the desired values in the application. Use simulation mode to test and determine the desired codes for the second stage gain, first stage gain, and output offset. The nominal values ...
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FILTERING FUNCTION The AD8555’s FILT/DIGOUT pin can be used to create a sim- ple low-pass filter. The AD8555’s internal 18 kΩ resistor can be used with an external capacitor for this purpose. Typical responses of the AD8555, configured for a ...
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AD8555 ±2. 100 S 0 0.1 1.0 LOAD CAPACITANCE (nF) Figure 58. Negative Overshoot Graph vs INTERFERENCE All instrumentation amplifiers show dc offset ...
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The bridge circuit with a sensitivity of 2 mV/V is excited supply. The full-scale output voltage from the bridge (±10 mV) therefore has a common-mode level of 2.5 V. The AD8555 removes the common-mode component and ...
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... AD8555ACPZ-R2 −40°C to +125°C 1 AD8555ACPZ-REEL −40°C to +125°C 1 AD8555ACPZ-REEL7 −40°C to +125° RoHS Compliant Part. ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 (0.1968) 4.80 (0.1890) ...