LTC695CSW#PBF Linear Technology, LTC695CSW#PBF Datasheet - Page 9

• Manufacturer Part Number: LTC695CSW#PBF
• Description: IC MPU SUPERVISRY CIRCUIT 16SOIC
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC695CSW#PBF

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Elements: 1
• Monitored Voltage 1 (typ): 4.65V
• Battery Backup Switching: Yes
• Watchdog Timer: Yes
• Chip Enable Signals: Yes
• Reset Active Time: 280ms
• Manual Reset: No
• Package Type: SOIC W
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.75V
• Reset Threshold Voltage (min): 4.5V
• Family Name: LTC695
• Power Dissipation: 500mW
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Power Fail Detection: Yes
• Mounting: Surface Mount
• Pin Count: 16
• Supply Current: 1.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Microprocessor Reset
The LTC690 family uses a bandgap voltage reference and a
precision voltage comparator C1 to monitor the 5V supply
input on V
the reset voltage threshold, the RESET output is forced
to active low state. The reset voltage threshold accounts
for a 5% variation on V
active low when V
On power-up, the RESET signal is held active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/LTC695) after reset voltage threshold is reached to
allow the power supply and microprocessor to stabilize.
The reset active time is adjustable on the LTC691/LTC695.
On power-down, the RESET signal remains active low
even with V
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V
not activate the RESET output. Response time is typically
10μs. To help prevent mistriggering due to transient loads,
V
the leads trimmed as short as possible.
The LTC691 and LTC695 have two additional outputs:
RESET and LOW⎯LINE. RESET is an active high output
and is the inverse of RESET. LOW⎯LINE is the output
of the precision voltage comparator C1. When V
CC
pin should be bypassed with a 0.1μF capacitor with
CC
CC
(see Block Diagram). When V
as low as 1V. This capability helps hold the
LOW LINE
RESET
CC
V
CC
falls below 4.75V (4.65V typical).
CC
, so the RESET output becomes
V2
t
1
CC
falls below
CC
Figure 1. Reset Active Time
CC
pin do
falls
V1
V2
below the reset voltage threshold, LOW⎯LINE goes low.
LOW⎯LINE returns high as soon as V
reset voltage threshold.
Battery Switchover
The battery switchover circuit compares V
input, and connects V
V
comparator, C2, connects V
pumped NMOS power switch, M1. When V
above V
switch, M2. C2 has typically 20mV of hysteresis to prevent
spurious switching when V
The response time of C2 is approximately 20μs.
During normal operation, the LTC690 family uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to V
5Ω. The V
0.1μF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
When operating currents larger than 50mA are required
from V
is desired, the LTC691 and LTC695 should be used. These
products provide BATT ON output to drive the base of
CC
rises to 70mV above V
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
t
1
OUT
= RESET ACTIVE TIME
BATT
t
RESET THRESHOLD HYSTERESIS
1
, or a lower dropout (V
OUT
OUT
, C2 connects V
pin should be bypassed with a capacitor of
from V
CC
OUT
and has a typical on resistance of
LTC690/LTC691
LTC694/LTC695
CC
to whichever is higher. When
OUT
OUT
BATT
remains nearly equal to V
CC
to V
, the battery switchover
to V
-V
V1
OUT
BATT
CC
690 F01
CC
voltage differential)
through a charge
through a PMOS
rises above the
CC
CC
falls to 50mV
to the V
BATT
BATT
9
690fe
.