MAX809SN120T1G ON Semiconductor, MAX809SN120T1G Datasheet - Page 8

• Manufacturer Part Number: MAX809SN120T1G
• Description: IC MPU RESET MON 1.20V SOT-23
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of MAX809SN120T1G

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 1.2V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-3, TO-236-3, Micro3™, SSD3, SST3
• Monitored Voltage: 1.2 V to 4.9 V
• Undervoltage Threshold: 1.2 V
• Output Type: Push-Pull
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 0.8 uA
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Overvoltage Threshold: 1.22 V
• Power-up Reset Delay (typ): 460 ms
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detail Operation Description
supervisory circuits are designed to monitor the power
supplies in digital systems and provide a reset signal to the
processor without any external components. Figure 2 shows
the timing diagram and a typical application below. Initially
consider that input voltage V
than the voltage detector upper threshold (
state for MAX809, or in the low state for MAX 810 devices.
RESET
The
(RESET)
MAX809/810
output voltage (Pin 2) will be in the high
Reset Output
MAX809, NCP803
Reset Output
MAX810
Input Voltage
series
CC
is at a nominal level greater
microprocessor
V
V
V
V
V
0V
V
V
0V
CC
TH+
TH–
CC
TH–
CC
TH–
V TH
Figure 15. Timing Waveforms
). And the
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reset
8
If there is an input power interruption and V
significantly deficient, it will fall below the lower detector
threshold (V
in the low state for the MAX809, or in the high state for the
NCP810 devices. After completion of the power
interruption, V
greater than the V
oscillator circuitry and digital counter to count. After the
count of the timeout period, the reset output will revert back
to the original state.
t
RP
TH−
CC
). This event causes the RESET output to be
will rise to its nominal level and become
TH
. This sequence activates the internal
CC
becomes