MAX6796TPLD4+T Maxim Integrated Products, MAX6796TPLD4+T Datasheet - Page 18

• Manufacturer Part Number: MAX6796TPLD4+T
• Description: IC REG LIN W/SPR VSR 20-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Regulator/Supervisorr

Specifications of MAX6796TPLD4+T

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.625V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TQFN Exposed Pad
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 72 V
• Output Voltage: 1.8 V to 11 V, 5 V
• Output Type: Adjustable, Fixed
• Dropout Voltage (max): 0.13 V at 20 mA
• Output Current: 300 mA
• Line Regulation: 1 %
• Load Regulation: 2 %
• Maximum Power Dissipation: 2.6667 W
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Voltage, Micropower, Single/Dual Linear
Regulators with Supervisory Functions
The watchdog timeout period is adjustable to accommo-
date a variety of µP applications. With this feature, the
watchdog timeout can be optimized for software execu-
tion. The programmer can determine how often the
watchdog timer should be serviced. Adjust the watch-
dog timeout period (t
between CSWT and GND. For normal-mode operation,
calculate the watchdog timeout capacitor as follows:
where t
To select the internally fixed watchdog timeout period
for the MAX6791–MAX6794, connect CSWT to OUT1.
To select the internally fixed watchdog timeout period
for the MAX6795/MAX6796, connect CSWT to OUT.
C
Ceramic capacitors are recommended; do not use
capacitors lower than 100pF to avoid the influence of
parasitic capacitances.
The MAX6791/MAX6792 have a windowed watchdog
timer that asserts RESET for t
recognizes a fast watchdog fault (time between transi-
tions < t
transitions > t
ed independently of the watchdog timeout period. The
slow watchdog period, t
where t
Figure 3. Windowed Watchdog Timing Diagram
18
CSWT
______________________________________________________________________________________
WD
WD2
must be a low-leakage (< 10nA) type capacitor.
WD1
Selecting Watchdog Timeout Period
t
t
WD
is in seconds and C
WD
is in seconds and C
), or a slow watchdog fault (time between
WD2
2
2
RESET:
WDI INPUT:
=
=
). The reset timeout period is adjust-
C
C
CSWT
CSWT
WD
WD2
) by connecting a capacitor
t
WD0






155
155
, is calculated as follows:
GUARANTEED
TO ASSERT
CSWT
RP
CSWT
×
×
when the watchdog
10
10
MIN
is in Farads.
6
UNDETERMINED
is in Farads.
6
V
A
t
V
A
WD1






MAX
TO NOT ASSERT
GUARANTEED
The fast watchdog period, t
from the slow watchdog fault period (t
fast watchdog period by connecting WDS0 and WDS1 to
OUT/OUT1 or GND according to Table 4, which illus-
trates the settings for the 8, 16, and 64 window ratios
(t
WDS0 and WDS1 are low, then t
t
has two edges too close to each other (faster than t
or has edges that are too far apart (slower than t
All WDI inputs are ignored while RESET is asserted. The
watchdog timer begins to count after RESET is
deasserted. If the time difference between two transi-
tions on WDI is shorter than t
RESET is forced to assert low for the reset timeout peri-
od. If the time difference between two transitions on WDI
is between t
and t
deassert; see Figure 3. To guarantee that the window
watchdog does not assert RESET, strobe WDI between
t
cleared when RESET is asserted. Disable the watchdog
timer by connecting WDS0 high and WDS1 low.
There are several options available to disable the
watchdog timer (for system development or test pur-
poses or when the µP is in a low-power sleep mode).
One way to disable the watchdog timer is to drive
WD-DIS low for the MAX6793–MAX6796 and drive
WDS0 high and WDS1 low for the MAX6791/MAX6792.
This prevents the capacitor from ramping up. Finally,
reducing the OUT/OUT1 regulator current below the
specified regulator current watchdog-disable threshold
(3mA min) also disables the watchdog timer. The
WD1
WD1
MIN
WD2
UNDETERMINED
t
WD2
WD2
is 40ms (typ). RESET asserts if the watchdog input
/t
(max) and t
WD1
MAX
(max), RESET is not guaranteed to assert or
). For example, if C
WD1
GUARANTEED
TO ASSERT
(min) and t
WD2
(min). The watchdog timer is
WD1
WD1
WD1
FAST
FAULT
NORMAL
OPERATION
SLOW
FAULT
, is selectable as a ratio
WD2
CSWT
(max) or t
or longer than t
is 318ms (typ) and
WD2
is 2000pF, and
). Select the
WD2
WD2
WD1
(min)
WD2
).
);
,