IR3856MTRPBF International Rectifier, IR3856MTRPBF Datasheet - Page 17

• Manufacturer Part Number: IR3856MTRPBF
• Description: IC BUCK SYNC ADJ 6A 17PQFN
• Manufacturer: International Rectifier
• Series: SupIRBuck™r
• Type: Step-Down (Buck)r

Specifications of IR3856MTRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.7 ~ 18.9 V
• Current - Output: 6A
• Frequency - Switching: 250kHz ~ 1.5MHz
• Voltage - Input: 1.5 ~ 21 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 17-PowerVQFN
• Power - Output: 1.11W
• Primary Input Voltage: 21V
• No. Of Outputs: 1
• Output Voltage: 18.9V
• Output Current: 6A
• No. Of Pins: 17
• Operating Temperature Range: -40°C To +125°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Part Status: Preferred
• Package: PQFN / 4 x 5
• Circuit: Single Output
• Iout (a): 6
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 21
• Output Range (v): 0.7 - 0.9*Vin
• Ocp Otp Uvlo Pre-bias Soft Start And: PGOOD + EN + SEQ + OVP + SYNC
• Design Tool: Yes
• Server Storage: Yes
• Routers Switches: Yes
• Base Station Telecom: Yes
• Digital Home Media: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Synchronization
The IR3856 incorporates an internal circuit which
enables synchronization of the internal oscillator
(using rising edge) to an external clock. An
external resistor from Rt pin to Gnd is still
required to set the free-running frequency close
to the Sync input frequency. This function is
important to avoid sub-harmonic oscillations due
to beat frequency for embedded systems when
multiple POL (point of load) regulators are used.
The synchronization clock can be applied during
IR3856 normal operation or before IR3856 start-
up. In any case, IR3856 will perform with the
external after the end of the PreBias cycle.
Applying the external signal to the Sync input
changes the effective value of the ramp signal
(Vramp/Vosc).
V
Equation (5) shows that the effective amplitude
of the ramp (V
Sync signal is applied. More difference between
osc
Rev2.0
(
eff
)
=
1 ×
.
8
osc(eff)
f
Free
_
) is reduced after the external
TIMING DIAGRAM OF Over Voltage Protection
Run
f
Sync
..........
Fig.10 IR3856 Over Voltage Timing Diagram
..........
....
(5)
the frequency of the Sync (f
running frequency (f
change in the effective amplitude of the ramp
signal.
Therefore, since the ramp amplitude takes part in
calculating the loop-gain and bandwidth of the
regulator, it is recommended not to use a Sync
frequency which is much higher than the free-
running frequency. In addition, the effective value
of the ramp signal, given by equation (5), should
be used when the compensator is designed for
the regulator.
The pulse width of the external clock, which is
applied to the sync, should be greater than 100ns
and its high level should be greater than 2V,
while its lower level is less than 0.6V. If this pin is
left floating, the IC will run with the free running
frequency set by the resistor Rt.
Free_Run
IR3856MPbF
) results in more
Sync
) and the free-
PD-97528
17