73M1966B-DB-C Maxim Integrated Products, 73M1966B-DB-C Datasheet - Page 47

• Manufacturer Part Number: 73M1966B-DB-C
• Description: BOARD DEMO 73M1966B CBL 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of 73M1966B-DB-C

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS_1x66B_001
8.2
The 73M1x66B supports the following PCLK input frequencies:
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The 73M1x66B automatically detects the frequency of PCLK and adjusts its internal PLL parameters
accordingly. At startup, the first eight frames are discarded. The next eight frames are used to count the
number of PCLK cycles during each frame. If the count differs among these eight frames or if the count is
a non-supported value, then a PCLKDT interrupt is asserted.
If PCLK is set at a frequency different from the above list, the PLL will be set for a PCLK of 2.048 MHz.
Since there will be a discrepancy between the frequency of PCLK and the frequency considered for PLL
settings, a PCLKDT interrupt may occur if required. It takes about 20 PCM frames before PLL is locked,
which is shown through the assertion of the FRCVCO status bit. PCLK must be running for several
cycles when reset is de-asserted. After that point, SPI transactions can start.
8.3
The default mode of operation for the PCM highway in the 73M1x66B is the slave mode i.e., FS and
PCLK are inputs to the device. The 73M1x66B offers a master mode by which a 4.096 MHz clock is
applied to the PCLKI pin. The master clock is divided by two to generate a 2.048 MHz clock that is
connected to the PCM highway via the PCLKO pin. Similarly, FS of one 2.048 MHz period long is
generated and driven to the PCM highway.
The master mode is set by setting the MASTER bit.
8.4
The 73M1x66B may be programmed for compressed A-law mode, compressed μ-law mode, or linear
mode. Compression schemes are used to minimize the bandwidth required for exchanging data samples
on the PCM highway. For instance, when PCLK is 8.192 MHz there are 128 8-bit time slots available.
The density of the overall system is halved when working in linear mode, which requires 16-bit time slots.
The 73M1x66B fully complies with the A-law and μ-law companding specifications defined in the ITU-T
Recommendation G.711.
Rev. 1.6
256 kHz
512 kHz
768 kHz
1.024 MHz
1.536 MHz
1.544 MHz
2.048 MHz
3.088 MHz
4.096 MHz
6.176 MHz
8.192 MHz
PCM Clock Frequencies
Master Mode
A-law / μ-law Compander
73M1866B/73M1966B Data Sheet
47