CK-S6-SP623-G Xilinx Inc, CK-S6-SP623-G Datasheet
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SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG751 (v1.1) September 15, 2010 ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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... User DIP Switches (Active High User Push Buttons (Active High User Test I GTP Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 GTP Transceiver Clock Input SMAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB to UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FMC HPC Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Management ...
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UG751 (v1.1) September 15, 2010 SP623 Board User Guide ...
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About This Guide This document describes the basic setup, features, and operation of the SP623 Spartan-6® FPGA GTP transceiver characterization board. The SP623 board provides the hardware environment for characterizing and evaluating the GTP transceivers available on the Spartan-6 XC6SLX150T-3FGG676 ...
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Preface: About This Guide Convention Courier font Courier bold Helvetica bold Italic font Online Document The following conventions are used in this document: Convention Blue text Blue, underlined text 6 Meaning or Use Messages, prompts, and program files that the ...
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... System ACE™ controller • Power module supporting all Spartan-6 FPGA GTP transceiver power requirements • A fixed, 200 MHz 2.5V LVDS oscillator wired to global clock inputs • One pair of global clock inputs with SMA connectors • SuperClock-2 module supporting multiple frequencies • ...
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... User GPIO 200 MHz LVDS Clock, Push Buttons, DIP Switches, and LEDs SuperClock-2 Module Figure 1-1: SP623 Board Block Diagram Figure 1-2 is described in the sections that follow. Figure 1-2 is for reference only and might not reflect the current revision of the www.xilinx.com ...
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... Configuration address DIP switch (SW3) 9 JTAG isolation jumpers (J22, J23, J195, J196) 10 200 MHz 2.5V LVDS oscillator (U7) 11 SuperClock-2 module 12 User SMA global clock inputs (J167, J168) 13 User LEDs, active-High (DS10 - DS17) 14 User DIP switches, active-High (SW1 - SW8) 15 User push buttons, active-High (SW4, SW6) 16 ...
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... ATX connector (J141) 1d: Power regulation jumpers (J30, J31, J33, J102, J104, J105) 1e: Regulation inhibit (J14, J19) 1f: External power supply jacks (J5, J98, J173, J174, J175, J177, J178, J189, J220, J223, J227, J234) 1g: TI PMBus cable connector (J6) 1h: GTP power supply module ...
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... Switching Module PTD08A020W 3.3V at 20A max PTV12010WAD DC-DC Converter 5. max Figure 1-3: SP623 Board Power Supply Block Diagram The SP623 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1-1 ...
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... Each power rail has a corresponding jack and jumper that is used to supply voltage to the rail using an external power supply. The jack, jumper, and regulator for each power rail is ...
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... MGTAVCC 1.2V 16A MGTAVTT 1.2V 12A The GTP transceiver power rails also have corresponding input voltage jacks to supply each voltage independently from a bench-top power supply (See External Supply Jack column in SP623 Board User Guide UG751 (v1.1) September 15, 2010 Figure Figure 1-4: Mounting Location, GTP Transceiver Power Module ...
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... Note: The power regulation jumper must be placed in the OFF position before connecting an external supply to its corresponding supply jack. The Texas Instruments and Intersil modules do not have voltage regulation jumpers and must be removed from the board before providing external power to the GTP transceiver rails ...
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Note: The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV cable is used, causing no disruption in the JTAG chain. The JTAG chain of the board is illustrated in isolation jumpers described in ...
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... The onboard System ACE controller (U25) allows storage of multiple configuration files on a CompactFlash card. These configuration files can be used to program the FPGA. The CompactFlash card connects to the CompactFlash card connector (U24) located directly below the System ACE controller on the back-side of the board. System ACE Controller Reset [Figure 1-2, callout 7] Pressing push button SW2 (RESET) resets the System ACE controller ...
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... The SuperClock-2 module connects to the clock module interface connector (J32) and provides a programmable, low-noise clock source for the SP623 board. The clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1 reset pin. Table 1-6 The SP623 board also supplies VCC5, VCC3V3, VCC2V5, and VCCO input power to the clock module interface ...
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... Chapter 1: SP623 Board Features and Operation Table 1-6: SuperClock-2 FPGA I/O Mapping FPGA Pin F12 E12 V12 W12 G12 F11 U25 U26 U20 U19 AA24 AA23 T20 T19 U22 U21 AE26 AE25 Y26 Y24 AC26 AC25 AB26 AB24 AD26 AD24 AA26 ...
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... These clock inputs can alternatively be used as a differential pair. The FPGA clock pins are connected to the SMAs as shown in Table 1-7. Note: Jumpers should NOT be installed on AFX SEL headers J99 and J100 if these clock inputs are used. Table 1-7: SMA Clock Input Connections FPGA Pin R25 ...
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Chapter 1: SP623 Board Features and Operation Table 1-9: User DIP Switches FPGA Pin J26 J25 K26 K24 G26 G25 H26 H24 User Push Buttons (Active High) [Figure 1-2, callout 15] SW5 and SW6 are active-High user push buttons that ...
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... GTP transceivers are grouped into four sets of two (referred to as Duals) which share two differential reference clock pin-pairs corresponding SMA connector are identified in X-Ref Target - Figure 1-8 123 Clocks 101 Clocks Figure 1-8: GTP Transceiver and Reference Clock SMA Locations Table 1-12: GTP Transceiver Pins FGPA Pin ...
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Chapter 1: SP623 Board Features and Operation Table 1-12: GTP Transceiver Pins (Cont’d) FGPA Pin B8 A8 D17 C17 B18 A18 D19 C19 B20 A20 AC8 AD8 AE7 AF7 AC10 AD10 AE9 AF9 AC18 AD18 AE19 AF19 AC20 AD20 AE21 ...
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... The SP623 board provides differential SMA connectors that can be used for connecting an external function generator to all GTP transceiver reference clock inputs of the FPGA. The FPGA reference clock pins are connected to the SMA connectors as shown in Table 1-13: GTP Transceiver Clock Inputs to the FPGA ...
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... The SP623 board features two high pin count (HPC) connectors as defined by the VITA 57.1.1 FMC specification. Each FMC HPC connector position socket that is fully populated with 400 pins. See cross-reference of signal names to pin coordinates. The FMC1 HPC connector at J112 on the SP623 board provides connectivity for: • ...
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... LA pairs • pairs • 2 differential clocks Note: The V (non-adjustable). The 2.5V rail cannot be turned off. The VITA 57.1 FMC interfaces on the SP623 board are compatible with 2.5V mezzanine cards capable of supporting 2.5V V The connections for the FMC1 and FMC2 connectors are identified in Table 1-18, respectively ...
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Chapter 1: SP623 Board Features and Operation Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin L10 ...
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Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin D13 C13 A13 H10 G10 B4 A4 F10 E10 J11 G11 H12 G13 K12 ...
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Chapter 1: SP623 Board Features and Operation Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin B12 A12 J16 J17 F16 E16 C3 B3 G15 F15 F18 E18 G16 F17 F20 E20 H17 G17 C21 B21 G6 ...
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... AB3 AB1 AD3 AD1 AC2 AC1 AE2 SP623 Board User Guide UG751 (v1.1) September 15, 2010 Net Name FMC Pin FMC1_LA33_N G37 FMC1_PRSNT_M2C H2 (1) FMC1_TCK_BUF D29 (1) FMC1_TDI D30 (1) FMC1_TDO D31 (1) TMS_BUF D33 Net Name FMC Pin FMC2_CLK0_M2C_P H4 FMC2_CLK0_M2C_N H5 FMC2_CLK1_M2C_P G2 FMC2_CLK1_M2C_N G3 FMC2_HA00_CC_P F4 FMC2_HA00_CC_N ...
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Chapter 1: SP623 Board Features and Operation Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin AE1 AA2 AA1 R10 ...
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Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin AE13 AF13 V18 W19 W17 W18 AA21 AB21 Y17 AA17 U15 V16 AA19 AB19 W16 Y16 AA18 AB17 Y15 AA16 V14 V15 U13 V13 AA15 AB15 Y21 AA22 ...
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Chapter 1: SP623 Board Features and Operation Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin AF15 AD23 AF23 Y11 AA11 V11 V10 AA9 AB9 AA10 AB11 AD6 AF6 W20 Y20 W10 W9 AE5 AF5 Y9 AA8 ...
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... The I C bus is controlled through U14, a four-channel I Instruments PCA9544A). The FPGA communicates with the multiplexer through I and clock signals mapped to FPGA pins J24 and J23, respectively. The I PCA9544A device is 0x70. The bus hosts four components: • GTP transceiver power supply module • ...
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Chapter 1: SP623 Board Features and Operation 34 www.xilinx.com UG751 (v1.1) September 15, 2010 SP623 Board User Guide ...
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... Default Jumper Positions Table A-1 shows the 23 standard (black) shunts that must be installed on the board for proper operation. There are an additional six (red) shorting plugs that must be installed to enable the output of on-board, regulated power and to connect the MGTAVCCPLL and MGTAVCC rails. These shunts and shorting plugs must always be installed except where specifically noted in this user guide ...
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Appendix A: Default Jumper Positions Table A-1: Standard Shunts (Cont’d) Connector Name J37 FMC2 JTAG Notes: These entries are not visible in the PCB silkscreen labels. 1. Table A-2: Digital Power Shorting Plugs Connector J3 J30 J31 J102 J104 J105 ...
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... LA18_N_CC GND DP1_C2M_N LA23_N GND DP9_C2M_P GND GND DP9_C2M_N LA26_P LA27_P GND DP2_C2M_P LA26_N LA27_N GND DP2_C2M_N GND GND DP8_C2M_P TCK GND DP8_C2M_N TDI SCL GND DP3_C2M_P TDO SDA GND DP3_C2M_N 3P3VAUX GND DP7_C2M_P TMS GND DP7_C2M_N TRST_L GA0 GND DP4_C2M_P ...
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Appendix B: VITA 57.1 FMC HPC Connector Pinout 38 www.xilinx.com UG751 (v1.1) September 15, 2010 SP623 Board User Guide ...
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SP623 Master UCF Listing The SP623 master user constraints file (UCF) template provides for designs targeting the SP623 Spartan-6 FPGA GTP transceiver characterization board. Net names in the constraints listed below correlate with net names on the SP623 board schematic. ...
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Appendix C: SP623 Master UCF Listing NET "245_RX1_P" NET "245_TX0_N" NET "245_TX0_P" NET "245_TX1_N" NET "245_TX1_P" NET "267_REFCLK0_N" NET "267_REFCLK0_P" NET "267_REFCLK1_N" NET "267_REFCLK1_P" NET "267_RX0_N" NET "267_RX0_P" NET "267_RX1_N" NET "267_RX1_P" NET "267_TX0_N" NET "267_TX0_P" NET "267_TX1_N" NET "267_TX1_P" ...
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... NET "DUT_PMB_CTRL" NET "DUT_PMB_DATA" NET "DUT_SPI_CS" NET "DUT_SPI_D" NET "DUT_SPI_Q" NET "DUT_SPI_SCK" NET "FMC1_CLK0_M2C_N" NET "FMC1_CLK0_M2C_P" NET "FMC1_CLK1_M2C_N" NET "FMC1_CLK1_M2C_P" NET "FMC1_CLK2_M2C_N" NET "FMC1_CLK2_M2C_P" NET "FMC1_HA00_CC_N" NET "FMC1_HA00_CC_P" NET "FMC1_HA01_CC_N" NET "FMC1_HA01_CC_P" NET "FMC1_HA02_N" NET "FMC1_HA02_P" NET "FMC1_HA03_N" NET "FMC1_HA03_P" NET "FMC1_HA04_N" ...
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Appendix C: SP623 Master UCF Listing NET "FMC1_HA23_P" NET "FMC1_LA00_CC_N" NET "FMC1_LA00_CC_P" NET "FMC1_LA01_CC_N" NET "FMC1_LA01_CC_P" NET "FMC1_LA02_N" NET "FMC1_LA02_P" NET "FMC1_LA03_N" NET "FMC1_LA03_P" NET "FMC1_LA04_N" NET "FMC1_LA04_P" NET "FMC1_LA05_N" NET "FMC1_LA05_P" NET "FMC1_LA06_N" NET "FMC1_LA06_P" NET "FMC1_LA07_N" NET "FMC1_LA07_P" ...
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NET "FMC1_LA29_N" NET "FMC1_LA29_P" NET "FMC1_LA30_N" NET "FMC1_LA30_P" NET "FMC1_LA31_N" NET "FMC1_LA31_P" NET "FMC1_LA32_N" NET "FMC1_LA32_P" NET "FMC1_LA33_N" NET "FMC1_LA33_P" NET "FMC1_PRSNT_M2C" NET "FMC2_CLK0_M2C_N" NET "FMC2_CLK0_M2C_P" NET "FMC2_CLK1_M2C_N" NET "FMC2_CLK1_M2C_P" NET "FMC2_HA00_CC_N" NET "FMC2_HA00_CC_P" NET "FMC2_HA02_N" NET "FMC2_HA02_P" NET "FMC2_HA03_N" ...
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Appendix C: SP623 Master UCF Listing NET "FMC2_HA23_N" NET "FMC2_HA23_P" NET "FMC2_LA00_CC_N" NET "FMC2_LA00_CC_P" NET "FMC2_LA01_CC_N" NET "FMC2_LA01_CC_P" NET "FMC2_LA02_N" NET "FMC2_LA02_P" NET "FMC2_LA03_N" NET "FMC2_LA03_P" NET "FMC2_LA04_N" NET "FMC2_LA04_P" NET "FMC2_LA05_N" NET "FMC2_LA05_P" NET "FMC2_LA06_N" NET "FMC2_LA06_P" NET "FMC2_LA07_N" ...
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NET "FMC2_LA28_P" NET "FMC2_LA29_N" NET "FMC2_LA29_P" NET "FMC2_LA30_N" NET "FMC2_LA30_P" NET "FMC2_LA31_N" NET "FMC2_LA31_P" NET "FMC2_LA32_N" NET "FMC2_LA32_P" NET "FMC2_LA33_N" NET "FMC2_LA33_P" NET "FMC2_PRSNT_M2C" NET "HSWAPEN_0" NET "INIT_B_2" NET "IO_L36N_2_AA13" NET "IO_L36P_2_AB13" NET "IO_L39N_M3LDQSN_3_V1" LOC = "V1"; NET "IO_L39P_M3LDQS_3_V3" LOC ...
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Appendix C: SP623 Master UCF Listing 46 www.xilinx.com UG751 (v1.1) September 15, 2010 SP623 Board User Guide ...
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... DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics • UG380, Spartan-6 FPGA Configuration User Guide • UG385, Spartan-6 FPGA Packaging and Pinout Specifications • UG381, Spartan-6 FPGA SelectIO Resources User Guide • UG388, Spartan-6 FPGA Memory Controller User Guide • ...
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Appendix D: References 48 www.xilinx.com UG751 (v1.1) September 15, 2010 SP623 Board User Guide ...