AD9857/PCB Analog Devices Inc, AD9857/PCB Datasheet - Page 10

• Manufacturer Part Number: AD9857/PCB
• Description: BOARD EVAL FOR AD9857
• Manufacturer: Analog Devices Inc

Specifications of AD9857/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9857
• Lead Free Status / Rohs Status: Not Compliant

AD9857
Pin Number
35, 37, 38, 43,
48, 54, 58, 64
36, 39, 40, 42,
44, 47, 53, 56,
59, 61, 65
45
46
49
50
55
60
62
63
66
67
68
69
79
80
Mnemonic
AVDD
AGND
IOUT
IOUT
DAC_BP
DAC_RSET
PLL_FILTER
DIFFCLKEN
REFCLK
REFCLK
DPD
RESET
PLL_LOCK
CIC_OVRFL
PDCLK/FUD
TxENABLE
I/O
O
O
I
O
I
I
I
I
I
O
O
I/O
I
Function
3.3 V Analog Power pin(s).
Analog Ground pin(s).
DAC Output pin. Normal DAC output current (analog).
DAC Complementary Output pin. Complementary DAC output current (analog).
DAC Reference Bypass. Typically not used.
DAC Current Set pin. Sets DAC reference current.
PLL Filter. R-C network for PLL filter.
Clock Mode Select pin. A logic high on this pin selects DIFFERENTIAL REFCLK input mode. A logic
low selects the SINGLE-ENDED REFCLK input mode.
Reference Clock pin. In single-ended clock mode, this pin is the Reference Clock input. In differential
clock mode, this pin is the positive clock input.
Inverted Reference Clock pin. In differential clock mode, this pin is the negative clock input.
Digital Power-Down pin. Assertion of this pin shuts down the digital sections of the device to
conserve power. However, if selected, the PLL remains operational.
Hardware RESET pin. An active high input that forces the device into a predefined state.
PLL Lock pin. Active high output signifying, in real time, when PLL is in lock state.
CIC Overflow pin. Activity on this pin indicates that the CIC Filters are in “overflow” state. This pin is
typically low unless a CIC overflow occurs.
Parallel Data Clock/Frequency Update pin. When not in single-tone mode, this pin is an output
signal that should be used as a clock to synchronize the acceptance of the 14-bit parallel
data-words on Pins D13–D0. In single-tone mode, this pin is an input signal that synchronizes the
transfer of a changed frequency tuning word (FTW) in the active profile (PSx) to the accumulator
(FUD = frequency update signal). When profiles are changed by means of the PS–PS1 pins, the FUD
does not have to be asserted to make the FTW active.
When TxENABLE is asserted, the device processes the data through the I and Q data pathways;
otherwise 0s are internally substituted for the I and Q data entering the signal path. The first data
word accepted when the TxENABLE is asserted high is treated as I data, the next data word is Q data,
and so forth.
Rev. C | Page 10 of 40