AD9857/PCB Analog Devices Inc, AD9857/PCB Datasheet - Page 26

• Manufacturer Part Number: AD9857/PCB
• Description: BOARD EVAL FOR AD9857
• Manufacturer: Analog Devices Inc

Specifications of AD9857/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD9857
• Lead Free Status / Rohs Status: Not Compliant

AD9857
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 6.
Table 6. Instruction Byte Information
MSB
R/W
R/ W
Bit 7 of the instruction byte determines whether a read or write
data transfer occurs after the instruction byte write. Logic high
indicates a read operation. Logic 0 indicates a write operation.
N1, N0
Bits 6 and 5 of the instruction byte determine the number of
bytes to be transferred during the data transfer cycle of the
communications cycle. The bit decodes are shown in Table 7.
Table 7. N1, N0 Decode Bits
N1
0
0
1
1
A4, A3, A2, A1, A0
Bits 4, 3, 2, 1, and 0 of the instruction byte determine which
register is accessed during the data transfer portion of the
communications cycle. For multibyte transfers, this address is
the starting byte address. The remaining register addresses are
generated by the AD9857.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK
Serial Clock. The serial clock pin is used to synchronize data to
and from the AD9857 and to run the internal state machines.
SCLK maximum frequency is 10 MHz.
CS
Chip Select. Active low input that allows more than one device
on the same serial communications lines. The SDO and SDIO
pins go to a high impedance state when this input is high. If
driven high during any communications cycle, that cycle is
suspended until CS is reactivated low. Chip Select can be tied
low in systems that maintain control of SCLK.
SDIO
Serial Data I/O. Data is always written into the AD9857 on this
pin. However, this pin can be used as a bidirectional data line.
The configuration of this pin is controlled by Bit 7 of register
address 00h. The default is logic zero, which configures the
SDIO pin as bidirectional.
SDO
Serial Data Out. Data is read from this pin for protocols that use
separate lines for transmitting and receiving data. When the
AD9857 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
D6
N1
N0
0
1
0
1
D5
N0
Transfer
1 byte
2 bytes
3 bytes
4 bytes
D4
A4
D3
A3
D2
A2
D1
A1
LSB
A0
Rev. C | Page 26 of 40
SYNCIO
Synchronizes the I/O port state machines without affecting the
addressable registers contents. An active high input on the
SYNC I/O pin causes the current communication cycle to abort.
After SYNC I/O returns low (Logic 0) another communication
cycle may begin, starting with the instruction byte write.
MSB/LSB Transfers
The AD9857 Serial Port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the Control Register 00h<6>bit.
The default value of Control Register 00h<6> is low (MSB first).
When Control Register 00h<6> is set high, the AD9857 serial
port is in LSB first format. The instruction byte must be written
in the format indicated by Control Register 00h<6>. That is, if
the AD9857 is in LSB first mode, the instruction byte must be
written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address of
the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB First mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
Notes on Serial Port Operation
The AD9857 serial port configuration bits reside in Bits 6 and 7
of register address 0h. It is important to note that the
configuration changes immediately upon writing to this register.
For multibyte transfers, writing to this register may occur
during the middle of a communication cycle. Care must be
taken to compensate for this new configuration for the
remainder of the current communication cycle.
The AD9857 serial port controller address rolls from 19h to 0h
for multibyte I/O operations if the MSB first mode is active. The
serial port controller address rolls from 0h to 19h for multibyte
I/O operations if the LSB first mode is active.
The system must maintain synchronization with the AD9857 or
the internal control logic is not able to recognize further
instructions. For example, if the system sends an instruction
byte for a 2-byte write, then pulses the SCLK pin for a 3-byte
write (8 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising
edges after the instruction cycle properly writes the first two
data bytes into the AD9857, but the next eight rising SCLK
edges are interpreted as the next instruction byte, not the final
byte of the previous communication cycle.