AD6650/PCB Analog Devices Inc, AD6650/PCB Datasheet
AD6650/PCB
Specifications of AD6650/PCB
Related parts for AD6650/PCB
AD6650/PCB Summary of contents
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FEATURES 116 dB dynamic range Digital VGA I/Q demodulators Active low-pass filters Dual wideband ADC Programmable decimation and channel filters VCO and phase-locked loop circuitry Serial data output ports Intermediate frequencies of 70 MHz to 260 MHz 10 dB noise ...
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AD6650 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Product Description......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Explanation of Test Levels ........................................................... 3 AC Specifications.......................................................................... 3 Digital Specifications ................................................................... 4 Electrical Characteristics............................................................. 5 General ...
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SPECIFICATIONS EXPLANATION OF TEST LEVELS I. 100% production tested. II. 100% production tested at 25°C; sample tested at specified temperatures. III. Sample tested only. IV. Parameter guaranteed by design and analysis. V. Parameter is typical value only. VI. 100% production ...
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AD6650 Parameter f = 150 MHz Coarse DC Correction 2 Noise Figure 2 Input IP2 Input IP3 2 Image Rejection Full-Scale Input Power Input Impedance f = 200 MHz Coarse DC Correction 2 Noise Figure 2 Input IP2 2 Input ...
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ELECTRICAL CHARACTERISTICS Table 3. Parameter (Conditions) LOGIC INPUTS Logic Compatibility Digital Logic Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CLOCK INPUTS 1 Differential Input Voltage Common-Mode Input Voltage Differential Input Resistance Differential Input ...
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AD6650 MICROPROCESSOR PORT TIMING CHARACTERISTICS All timing specifications valid over VDD range of 3 3.45 V and VDDIO range of 3 3.45 V. Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation Parameter WRITE ...
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TIMING DIAGRAMS RESET SDO0/SDO1 t SSF Figure 2. RESET Timing Requirements CLK t DSCLKH SCLK Figure 3. SCLK Switching Characteristics (Divide-by-1) CLK t t DSCLKH DSCLKL SCLK Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer) CLK t t DSCLKH ...
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AD6650 SYNC RD (DS) WR (R/W) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ACC FROM FALLING EDGE RISING EDGE OF RDY ACC RD (DS) WR (R/W) CS A[2:0] D[7:0] RDY (DTACK) NOTES t 1. ...
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DS (RD) R/W (WR SAM HAM VALID ADDRESS A[2: SAM HAM D[7:0] VALID DATA DTACK (RDY) t ACC NOTES t 1. ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED ACC FROM FALLING ...
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AD6650 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Input Voltage Output Voltage Swing Load Capacitance Junction Temperature Under Bias Storage Temperature Range Lead Temperature (5 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Configuration DGND TDI TMS SDFS SCLK TDO B C SDO1 SDO0 DVDD D7 DR DVDD DVDD DVDD DVDD ...
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AD6650 Mnemonic Type DTACK (RDY) Output R/W (WR) Input MODE [2:0] Input JTAG TRST Input TCLK Input TMS Input TDO Output TDI Input ANALOG INPUTS AIN Input Input AIN BIN Input BIN Input PLL INPUTS CPOUT Output LF Input VLDO ...
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TYPICAL PERFORMANCE CHARACTERISTICS 44 42 +25° –25° 110 130 150 170 IF FREQUENCY (MHz) Figure 15. Input IP2 vs. Frequency –6 –7 –8 –9 –10 +25°C –11 –25°C –12 –13 +85°C –14 ...
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AD6650 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Noise Figure (NF) The degradation in SNR performance (in dB ...
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EQUIVALENT CIRCUITS 1nH AIN/BIN 25Ω 75Ω CLAMP 1pF 2pF 75Ω 25Ω 1nH AIN/BIN Figure 19. Analog Input AVDD 20kΩ 20kΩ 5kΩ 2.5kΩ CLK 5pF 5kΩ 2.5kΩ CLK 20kΩ 20kΩ Figure 20. Clock Input Rev Page ...
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AD6650 THEORY OF OPERATION ANALOG FRONT END The AD6650 is a mixed-signal front-end (MxFE®) component intended for direct IF sampling radios requiring high dynamic range optimized for the demanding performance require- ments of GSM and EDGE. The AD6650 ...
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Coarse DC Correction The coarse dc correction block is a simple integrate-and-dump that integrates the data for 16,384 cycles at the ADC clock rate (typically 26 MSPS) and then updates an estimate of the dc. This estimate is then subtracted ...
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AD6650 INFINITE IMPULSE RESPONSE (IIR) FILTER The IIR filter of the AD6650 is a seventh-order low-pass filter with an infinite impulse response. This filter cannot be bypassed and always performs a decimation can be seen from the ...
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RCF Filter Length The maximum number of taps this filter can calculate, N given by Equation 10. The value N − written to the taps channel register within the AD6650 at Address 0x1B. ⎛ × ⎞ ...
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AD6650 0 –10 –20 –30 CIC4 RESPONSE –40 AD6650 DIGITAL COMPOSITE –50 RESPONSE –60 IIR FILTER –70 RESPONSE –80 –90 –100 –110 –120 –1.98 –1.46 –0.94 –0. FREQUENCY (MHz) Figure 26. Composite Digital Response with 8× Rate FINE ...
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Peak Detector The peak detector always stores the input sample with the largest magnitude. The absolute value of every input sample is compared to what is currently in the peak detector’s holding register. The only exception is when the control ...
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AD6650 LO SYNTHESIS The AD6650 has a fully integrated quadrature LO synthesizer consisting of a voltage-controlled oscillator (VCO) and a phase- locked loop (PLL). Together these blocks generate quadrature IF LO signals for the demodulators. Figure 27 shows a block ...
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LF CP 200Ω AD6650 1.0µF VLDO Figure 28. Loop Filter Circuit R-DIVIDER CLR1 U3 ADP2 ADP1 CLR2 DOWN N-DIVIDER R-DIVIDER N-DIVIDER CP OUTPUT Figure 29. PFD Simplified Schematic and Timing (Locked) ...
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AD6650 value is −40 dBFS. When the wideband signal is below the SPB level, the FD loop is activated. This loop overrides the slow loop and has a programmable step size (default 0.094 dB) and a programmable peak detect period ...
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SDO SDO is the serial data output. Serial output data is shifted on the rising edge of SCLK. On the next SCLK rising edge after an SDFS, the MSB of the I data from the channel is shifted. On every ...
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AD6650 APPLICATION INFORMATION REQUIRED SETTINGS AND START-UP SEQUENCE FOR DC CORRECTION On startup, the fine dc correction block may take up to several minutes to converge to a good dc estimate, especially if a large signal is present on the ...
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Another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 37. A device that offers excellent jitter performance is the MC100EL16 (or a device from the same family) from Motorola. VT 0.1µF ...
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AD6650 –35 –40 –45 –50 –55 –60 –65 –70 – 100 OFFSET FREQUENCY (kHz) Figure 40. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz) An additional parameter that strongly impacts the PSRR is the sensitivity to ...
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CHIP SYNCHRONIZATION The AD6650 is designed to allow synchronization of multiple AD6650s within a system. The AD6650 is synchronized with either a microprocessor write (Soft_SYNC pulse on the SYNC pin (Pin_SYNC). The first sync event starts the device, ...
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AD6650 MICROPORT CONTROL The AD6650 has an 8-bit microprocessor port. The microport interface is a multimode interface that allows flexibility when dealing with the host processor. There are two modes of bus operation: Intel® nonmultiplexed mode (INM) and Motorola nonmultiplexed ...
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Table 14. Microport Instructions Instruction Description 0xxx All chips obtain access. 1000 All chips with Chip_ID [1: obtain access. 1001 All chips with Chip_ID [1: obtain access. 1100 All chips with Chip_ID [1: obtain ...
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AD6650 JTAG BOUNDARY SCAN The AD6650 supports a subset of the IEEE Standard 1149.1 specification. For details of the standard, see the IEEE Standard Test Access Port and Boundary-Scan Architecture, an IEEE-1149 publication. The AD6650 has five pins associated with ...
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REGISTER MAP Table 18. Memory Map Reg. Bit (Hex) Mnemonic Width 0 Clock Divider Control 1 1 PLL Register PLL Register PLL Register PLL Register Clamp Control 6 ...
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AD6650 Reg. Bit (Hex) Mnemonic Width B DC Correction Control 13: Upper 7 Threshold Lower Threshold Minimum Period 5 2: Bypass 1 1: Interpolate 1 0: Freeze 1 C AGC ...
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Reg. Bit (Hex) Mnemonic Width D AGC Control VGA Gain E AGC Control Hysteresis Requested Level 8 F AGC Control Loop ...
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AD6650 Reg. Bit (Hex) Mnemonic Width 10 AGC Control 10: FD_Step FA_Thresh FA_Count FA_Step 4 11 AGC Control SPB ...
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Reg. Bit (Hex) Mnemonic Width 14 Start Holdoff Counter 16 15 CIC4 Decimation (M − CIC4 16 CIC4 Scale (Scale − 12 IIR Control 1 18 RCF Decimation Register 3 (M − 1) RCF 19 RCF ...
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AD6650 Reg. Bit (Hex) Mnemonic Width 1B RCF Taps (N − Taps 1C RCF Scale 2 1D BIST for A BIST for A BIST for B BIST for B Serial ...
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REGISTER DETAILS Table 19. PLL Register 0: Control Latch CH Address Register Description DB21 to DB0 RSVD Reserved Table 20. PLL Register 1: R Counter Latch CH Address Register Description DB21 to DB14 RSVD Reserved DB13 to DB0 R1 to ...
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AD6650 0x0A: Coarse DC Correction Control Register [3:0] Address 0xA is the coarse dc correction control register used to enable the coarse correction with Bit 0 and to initiate calibrations on Channel A and/or Channel B. Bit 3 ...
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This is useful for debugging and for use when the dc estimate can be performed at discrete predefined times. Even though the upper threshold register can vary between 0 and 15 and the Min_period register can vary ...
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AD6650 The peak detector for this threshold monitors the desired signal and blocker peaks at the ADC output. 0x14: Start Holdoff Counter [15:0] The start holdoff counter is loaded with the value written to this address when a sync is ...
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Autocalibration Register [3:0] Address 0x22 is the autocalibration register and controls the automatic coarse dc autocalibration at start-up. Bit 3 Reserved. This bit should be set to 0. Bit 2 Reserved. This bit should be set to 1. Bit ...
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... AD6650BBC −25°C to +85°C 2 AD6650BBCZ −25°C to +85°C AD6650/PCB 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40° Pb-free part. ...