SDM-09120 Sirenza Microdevices Inc, SDM-09120 Datasheet - Page 2

• Manufacturer Part Number: SDM-09120
• Description: MODULE PWR AMP 120W 960MHZ AB
• Manufacturer: Sirenza Microdevices Inc

Specifications of SDM-09120

• Current - Supply: 1A
• Frequency: 925MHz ~ 960MHz
• Gain: 15dB
• P1db: 130W
• Package / Case: Module
• Rf Type: CDMA, GSM, EDGE
• Voltage - Supply: 28V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Noise Figure: -
• Test Frequency: -

303 S. Technology Court
Broomfield, CO 80021
Pin Description
Simplified Device Schematic
Absolute Maximum Ratings
Drain Voltage (V
RF Input Power
Load Impedance for Continuous Operation
Without Damage
Control (Gate) Voltage, VDD = 0 VDC
Output Device Channel Temperature
Operating Temperature Range
Storage Temperature Range
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
2,4,7,9
Flange
Pin #
10
1
3
5
6
8
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
RF Output
Function
RF Input
Ground
Ground
1
2
3
5
4
V
V
V
V
GS1
GS2
DD
D2
D1
)
Parameters
LDMOS FET Q1 and Q2 gate bias. V
Module Topside ground.
Internally DC blocked
LDMOS FET Q3 and Q4 gate bias. V
LDMOS FET Q3 and Q4 drain bias. See Note 1.
Internally DC blocked
LDMOS FET Q1 and Q2 drain bias. See Note 1.
Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures
optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for
Power Modules.
Q1
Q2
Q3
Q4
Phone: (800) SMI-MMIC
10
9
8
7
6
Value
-20 to
-40 to
+200
+100
+43
+90
5:1
35
15
GSTH
GSTH
3.0 to 5.0 VDC. See Notes 2, 3 and 4
3.0 to 5.0 VDC. See Notes 2, 3 and 4
2
VSWR
dBm
Unit
SDM-09120 925-960 MHz 130W Power Amp Module
ºC
ºC
ºC
V
V
Description
Note 1:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the V
accommodate modulated signals.
Note 2:
Gate voltage must be applied to V
or after application of drain voltage to prevent potentially
destructive oscillations. Bias voltages should never be applied
to a module unless it is properly terminated on both input and
output.
Note 3:
The required V
module to module and may differ between V
the same module by as much as ±0.10 volts due to the normal
die-to-die variation in threshold voltage for LDMOS transistors.
Note 4:
The threshold voltage (V
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
Note 5:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° F, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation instructions.
GS
corresponding to a specific I
GSTH
) of LDMOS transistors varies with
http://www.sirenza.com
EDS-103478 Rev G
GS
leads simultaneously with
D
leads to
GS1
DQ
and V
will vary from
GS2
on