EM35X-BBRD Ember, EM35X-BBRD Datasheet - Page 82

• Manufacturer Part Number: EM35X-BBRD
• Description: EM35X BREAKOUT BOARD
• Manufacturer: Ember

Specifications of EM35X-BBRD

• Frequency: 2.4GHz
• For Use With/related Products: EM35x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1013

The GPIO pins used for these signals are shown in Table 8-3. Additional outputs may be needed to drive the
nSSEL signals on slave devices.
8.3.2
Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following
register settings:
The SPI serial clock (SCLK) is produced by a programmable clock generator. The serial clock is produced by
dividing down 12 MHz according to this equation:
EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register.
The SPI master mode clock may not exceed 12 Mbps, so EXP and LIN cannot both be zero.
The SPI master controller supports various frame formats depending upon the clock polarity (SC_SPIPOL),
clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-4). The bits SC_SPIPOL, SC_SPIPHA,
and SC_SPIORD are defined within the SCx_SPICFG register.
Direction
GPIO Configuration
SC1 pin
SC2 pin
The serial controller mode register (SCx_MODE) is 2.
The SC_SPIMST bit in the SPI configuration register (SCx_SPICFG) is 1.
Set Up and Configuration
rate
=
(
Alternate Output
LIN
(push-pull)
12
Table 8-3. SPI Master GPIO Usage
+
Output
MOSI
MHz
1
PB1
PA0
* )
Final
8-7
2
EXP
MISO
Input
Input
PA1
PB2
EM351 / EM357
Alternate Output
(push-pull)
SCLK
Output
PB3
PA2
120-035X-000G