AD607ARSZ-REEL Analog Devices Inc, AD607ARSZ-REEL Datasheet - Page 17

• Manufacturer Part Number: AD607ARSZ-REEL
• Description: IC RECEIVER IF SUBSYS LP 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD607ARSZ-REEL

• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Function: Receiver IF Subsystem
• Frequency: 500MHz
• Secondary Attributes: -8dBm Input Third Order Intercept
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Frequency Range: 400kHz To 12MHz
• Supply Voltage Range: 2.92V To 5.5V
• Rf Ic Case Style: SSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Operating Supply Voltage: 3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff)
do not attenuate the IF or feedthrough products. Thus, the
maximum input voltage at DMIP must be limited to ± 75 mV
to allow sufficient headroom at the I and Q outputs for not only
the desired baseband signal, but also the unattenuated higher-
order demodulation products. These products can be removed
by an external low-pass filter. In the case of IS54 applications
using a 455 kHz IF and the AD7013 baseband converter, a simple
one-pole RC filter with its corner above the modulation band-
width is sufficient to attenuate undesired outputs.
Phase-Locked Loop
The demodulators are driven by quadrature signals that are
provided by a variable frequency quadrature oscillator (VFQO),
phase-locked to a reference signal applied to Pin FDIN. When
this signal is at the IF, in-phase and quadrature baseband outputs
REV. C
Figure 19. Suggested Methods for Biasing Pin DMIP
at V
a. Biasing DMIP from Power Supply (Assumes BPF
AC-Coupled Internally)
P
b. Biasing DMIP from VMID (Assumes BPF
AC-Coupled Internally)
/2
AD607
Power Supply
Voltage
(V)
3.0
3.5
4.0
4.5
5.0
5.5
Maximum gain occurs for gain control voltage = 0 V.
AD607
DMIP
IFOP
DMIP
VMID
IFOP
Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage
R
T
R
T
C
BYPASS
BPF
BPF
GREF
(= VMID)
(V)
1.5
1.75
2.0
2.25
2.5
2.75
R
VPOS
T
2R
2R
T
T
Scale Factor
(dB/V)
50.00
42.86
37.50
33.33
30.00
27.27
–17–
are generated at IOUT and QOUT, respectively. The quadra-
ture accuracy of this VFQO is typically –1.2°C at 10.7 MHz. The
PLL uses a sequential-phase detector that comprises low power
emitter-coupled logic and a charge pump (Figure 20).
The reference signal may be provided from an external source
in the form of a high level clock, typically a low level signal
(± 400 mV) since there is an input amplifier between FDIN and
the loop’s phase detector. For example, the IF output itself can
be used by connecting DMIP to FDIN, which will then provide
automatic carrier recover for synchronous AM detection and
take advantage of any post-IF filtering. Pin FDIN must be
biased at V
The VFQO operates from 400 kHz to 12 MHz and is controlled
by the voltage between VPOS and FLTR. In normal operation,
a series RC network forming the PLL loop filter is connected
from FLTR to ground. The use of an integral sample-hold
system ensures that the frequency-control voltage on Pin FLTR
remains held during power-down, so reacquisition of the carrier
typically occurs in 16.5 µs.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs
to be considered in making filter choices. This is typically 16.5 µs
at an IF of 10.7 MHz for a ±100 mV signal at DMIP and FDIN.
(FDIN AFTER LIMITING)
F
R
REFERENCE CARRIER
Figure 20. Simplified Schematic of the PLL and
Quadrature VCO
Scale Factor
(mV/dB)
20.00
23.33
26.67
30.00
33.33
36.67
SEQUENTIAL
DETECTOR
PHASE
P
/2; Figure 22 shows suggested methods.
U
D
Gain Control
Voltage Input Range
(V)
0.400–2.000
0.467–2.333
0.533–2.667
0.600–3.000
0.667–3.333
0.733–3.667
I
40 A
I
40 A
U
D
~
~
V
R
C
F
QUADRATURE
OSCILLATOR
FREQUENCY
VARIABLE-
AD607
(ECL OUTPUTS)
Q-CLOCK
I-CLOCK
90