AD6655BCPZ-80 Analog Devices Inc, AD6655BCPZ-80 Datasheet - Page 33

• Manufacturer Part Number: AD6655BCPZ-80
• Description: IC IF DIVERSITY RECEIVER 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-80

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 420mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 60. The
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516
drivers offer excellent jitter performance.
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS
gate, and the CLK− pin should be bypassed to ground with
a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 61).
CLK+ can be driven directly from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V, making the selection
of the drive logic voltage very flexible.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
50kΩ
50kΩ
Figure 59. Differential PECL Sample Clock (Up to 625 MHz)
Figure 60. Differential LVDS Sample Clock (Up to 625 MHz)
50Ω
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
50kΩ
V
V
CC
CC
1kΩ
1kΩ
1kΩ
1kΩ
PECL DRIVER
LVDS DRIVER
CMOS DRIVER
CMOS DRIVER
AD951x
AD951x
AD951x
AD951x
240Ω
0.1µF
OPTIONAL
OPTIONAL
240Ω
100Ω
100Ω
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD9510/
AD6655
AD6655
AD6655
AD6655
ADC
ADC
ADC
ADC
clock
Rev. A | Page 33 of 88
Input Clock Divider
The AD6655 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a divide
ratio other than 1 is selected, the duty cycle stabilizer is auto-
matically enabled.
The AD6655 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD6655 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD6655. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on, as
shown in Figure 44.
Jitter on the rising edge of the input clock is still of paramount
concern and is not easily reduced by the internal stabilization
circuit. The duty cycle control loop does not function for clock
rates less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered when the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time
period that the loop is not locked, the DCS loop is bypassed,
and internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications, enabling
the DCS circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 63.
SNR
HF
= −10 log[(2π × f
IN
) due to jitter (t
IN
J
) can be calculated by
× t
JRMS
)
2
+ 10
(
−
SNR
LF
/
10
AD6655
)
]