AD6655BCPZ-80 Analog Devices Inc, AD6655BCPZ-80 Datasheet - Page 46

• Manufacturer Part Number: AD6655BCPZ-80
• Description: IC IF DIVERSITY RECEIVER 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-80

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 420mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-150EBZ - BOARD EVAL FOR 150MSPS AD6655AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD6655
DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
control register located at Register 0x10C, Bits[5:2]. The following
equation can be used to compute the bandwidth value for the dc
correction circuit:
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x10C
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
f
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a
14-bit value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the DC correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction value
can be added to the output data signal path by setting Bit 1 of
Register 0x10C.
SMI SCLK
SMI SDFS
CLK
SMI SDO
SMI SCLK
SMI SDFS
SMI SDO
is the AD6655 ADC sample rate in hertz (Hz).
DC
_
Corr
_
BW
MSB
=
20 CYCLES
MSB
RMS/MS CH A
2
−
k
−
20 CYCLES
14
RMS/MS CH A
×
2
f
LSB
Figure 79. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
CLK
×
π
Figure 80. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
16 CYCLES
LSB
PK CH A
16 CYCLES
16 CYCLES
THR CH A
THR CH A
Rev. A | Page 46 of 88
MSB
MSB
20 CYCLES
20 CYCLES
RMS/MS CH B LSB
RMS/MS CH B
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins: the SMI
SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and SMI
SDO (SPORT data output). The SPORT is the master and drives
all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,
or 1/8 the ADC clock rate, based on the SPORT controls. The
SMI SCLK can also be gated off when not sending any data, based
on the SPORT SMI SCLK sleep bit. Using this bit to disable the
SMI SCLK when it is not needed can reduce any coupling errors
back into the signal path, if these prove to be a problem in the
system. Doing so, however, has the disadvantage of spreading
the frequency content of the clock. If desired the SMI SCLK
can be left running to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data is
sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more of rms magnitude,
peak level, and threshold crossing values from each datapath in
the stated order. If enabled, the data is sent, rms first, followed
by peak and threshold, as shown in Figure 79.
GATED, BASED ON CONTROL
LSB
GATED, BASED ON CONTROL
16 CYCLES
PK CH B
16 CYCLES
THR CH B
16 CYCLES
THR CH B
RMS/MS CH A
RMS/MS CH A