TEA5766UK/N1-T ST-Ericsson Inc, TEA5766UK/N1-T Datasheet - Page 34

• Manufacturer Part Number: TEA5766UK/N1-T
• Description: IC FM STEREO RADIO W/RDS 25WLCSP
• Manufacturer: ST-Ericsson Inc

Specifications of TEA5766UK/N1-T

• Frequency: 76MHz ~ 108MHz
• Sensitivity: -111dBm
• Modulation Or Protocol: FM
• Applications: FM Radio Receiver
• Current - Receiving: 17mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.6 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 25-WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Data Rate - Maximum: -
• Other names: 935281564118

NXP Semiconductors
Table 10.
[1]
TEA5766UK_1
Product data sheet
Symbol
V
V
t
of
Fig 16. I
OL1
OL3
BUSEN
The maximum fall time for the SDA and SCL bus lines quoted in table 5 of
output stages, 350 ns, therefore no series protection resistors may be connected between the SDA and SCL pins and the SDA and SCL
bus lines as shown in figure 36 of
SCL
SDA
In TEA5766UK, signal SDA is present on pin DATA and signal SCL on pin CLOCK.
C
t
t
t
t
t
t
t
Remark: 300 ns lower limit is added because the TEA5766UK has no internal hold time for the SDA signal.
t
t
t
t
t
f
r
HD;STA
HIGH
LOW
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
su(BUSEN)
h(BUSEN)
2
b
= fall time of both SDA and SCL signals: 20 + 0.1 C
= rise time of both SDA and SCL signals: 20 + 0.1 C
C-bus timing diagram
Characteristics of the data output stage for fast mode and standard mode
= capacitive load for each bus line: < 100 pF.
Parameter
LOW-level output
voltage
LOW-level output
voltage
output fall time
= bus free time between a STOP and a START condition: > 600 ns.
= LOW period of the SCL clock: > 1.3 s
P
= HIGH period of the SCL clock: > 600 ns.
10.2.3 I
t
= set-up time for a repeated START condition: > 600 ns.
= data set-up time: > 100 ns. If TEA5766UK is used in a standard mode I
= hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.
= data hold time: 300 ns < t
= set-up time for STOP condition: > 600 ns.
su(BUSEN)
= hold time on pin BUSEN: > 10 s.
= set-up time on pin BUSEN (bus enable): > 10 s.
t
BUF
2
C-bus timing diagram
S
t
HD;STA
Ref.
Conditions
open collector; I
fast mode; open collector; I
V
from V
t
SU;DAT
1.
VREFDIG
standard mode
fast mode
standard mode
fast mode
HD;DAT
IH(min)
< 900 ns.
t
< 2 V
HD;DAT
Rev. 01 — 22 March 2007
to V
sink
IL(max)
t
b
r
t
b
HIGH
= 2 mA; V
< t
< t
f
; C
t
f
< 350 ns, where C
f
< 350 ns, where C
b
t
sink
= 5 pF to 100 pF
LOW
VREFDIG
= 2 mA;
Ref.
1, 300 ns, is shorter than the specified maximum for the
> 2 V
b
b
= total capacitance on bus line in pF.
t
= total capacitance on bus line in pF.
SU;STA
2
C-bus system, t
[1]
Sr
Min
0
0
0
250
250
SU;DAT
TEA5766UK
Stereo FM radio + RDS
Typ
-
-
-
-
-
> 250 ns.
t
SU;STO
© NXP B.V. 2007. All rights reserved.
t
h(BUSEN)
Max
0.5
0.5
0.5
350
350
001aaf518
P
33 of 59
Unit
V
V
V
ns
ns