SI4705-C40-GM Silicon Laboratories Inc, SI4705-C40-GM Datasheet - Page 19

• Manufacturer Part Number: SI4705-C40-GM
• Description: IC RX FM RADIO 64-108MHZ 20UQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4705-C40-GM

• Frequency: 64MHz ~ 108MHz
• Modulation Or Protocol: FM
• Applications: General Purpose
• Current - Receiving: 19.9mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-UQFN, 20-µQFN
• Pin Count: 20
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In the analog audio output mode, pin 13 is ROUT, pin 14
is LOUT, and pin 17 is GPO3. In the digital audio mode,
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
Concurrent analog/digital audio output mode requires
pins 13, 14, 15, 16, and 17.
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I
three pins: digital data input (DIN), digital frame
synchronization
synchronization input clock (DCLK). The Si4704/05
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The Si4704/05 is reset by applying a logic low on RST
signal. This causes all register values to be reset to their
default values. The digital output interface supply (V
provides voltage to the RST, SEN, SDIO, RCLK, DOUT,
DFS, and DCLK pins and can be connected to the audio
baseband processor's supply voltage to save power and
remove the need for voltage level translators. RCLK is
not required for register operation.
The Si4704/05 reference clock is programmable,
supporting many RCLK inputs as shown in Table 11.
4.2. Application Schematics and Operating
The application schematic for the Si4704/05 is shown in
Section "2. Typical Application Schematic" on page 16.
The Si4704/05 supports selectable analog, digital, or
concurrent analog and digital audio output modes. In
the analog output mode, pin 13 is ROUT, pin 14 is
LOUT, and pin 17 is GPO3. In the digital output mode,
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
Concurrent analog and digital audio output mode
requires pins 13, 14, 15, 16, and 17. In addition to
output mode, there is a clocking mode to clock the
Si4704/05 from a reference clock or crystal oscillator.
The user sets the operating modes with commands as
described in Section "5. Commands and Properties" on
page 25.
4.3. FM Receiver
The Si4704/05 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture
components and factory adjustments. The Si4704/05
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (64 to 108 MHz). An
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An image-
reject mixer downconverts the RF signal to low-IF.
Modes
2
S and left-justified modes. The interface has
allowing
input
the
(DFS),
elimination
and
a
of
digital
external
IO
Rev. 1.0
bit
)
The quadrature mixer output is amplified, filtered, and
digitized
converters (ADCs). This advanced architecture allows
the Si4704/05 to perform channel selection, FM
demodulation, and stereo audio processing to achieve
superior performance compared to traditional analog
architectures.
4.4. Digital Audio Interface (Si4705 Only)
The digital audio interface operates in slave mode and
supports three different audio data formats:



4.4.1. Audio Data Formats
In I
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.4.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
I
Left-Justified
DSP Mode
2
2
S mode, by default the MSB is captured on the
S
with
high
Si4704/05-C40
resolution
analog-to-digital
19