PIC18LF24K22-I/SP Microchip Technology, PIC18LF24K22-I/SP Datasheet - Page 288

• Manufacturer Part Number: PIC18LF24K22-I/SP
• Description: IC PIC MCU 16KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24K22-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Processor Series: PIC18LF
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
16.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTAx register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXSTAx register configures the device
as a slave. Clearing the SREN and CREN bits of the
RCSTAx register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCSTAx register
enables the EUSART. If the RXx/DTx or TXx/CKx pins
are shared with an analog peripheral the analog I/O
functions must be disabled by clearing the corresponding
ANSEL bits.
RXx/DTx and TXx/CKx pin output drivers must be
disabled by setting the corresponding TRIS bits.
DS41412D-page 288
SYNCHRONOUS SLAVE MODE
Preliminary
16.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master
case of the Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
16.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREGx
register.
The TXxIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREGx register will transfer the
second character to the TSR and the TXxIF bit
will now be set.
If the PEIE/GIEL and TXxIE bits are set, the
interrupt will wake the device from Sleep and
execute the next instruction. If the GIE/GIEH bit
is also set, the program will call the Interrupt
Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE/GIEH
and PEIE/GIEL bits of the INTCON register are
set and set the TXxIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREGx register.
are
transmission
EUSART Synchronous Slave
Transmit
Synchronous Slave Transmission
Setup:
identical
 2010 Microchip Technology Inc.
Transmission”), except in the
by
(see
writing
Section 16.4.1.3
the
Least